| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-19 | Sygus streaming non-implied predicates (#2660) | Andrew Reynolds |
| 2018-10-17 | Sygus query generator (#2465) | Andrew Reynolds |
| 2018-10-09 | Support for basic actively-generated enumerators (#2606) | Andrew Reynolds |
| 2018-10-09 | Allow multiple synthesis conjectures. (#2593) | Andrew Reynolds |
| 2018-10-03 | Add actively generated sygus enumerators (#2552) | Andrew Reynolds |
| 2018-09-27 | Remove assertion. (#2549) | Andrew Reynolds |
| 2018-09-27 | Infrastructure for using active enumerators in sygus modules (#2547) | Andrew Reynolds |
| 2018-09-24 | Allow partial models for multiple sygus enumerators (#2499) | Andrew Reynolds |
| 2018-09-18 | Move and rename sygus solver classes (#2488) | Andrew Reynolds |
 |
index : cvc5.git | |
| CVC4 is an efficient open-source automatic theorem prover for satisfiability modulo theories (SMT) problems. | git repository hosting |
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