blob: ba46e18e25d2218aa5d2ed5ff5a766b2476f3a4b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
|
/********************* */
/*! \file theory.cpp
** \verbatim
** Original author: mdeters
** Major contributors: taking
** Minor contributors (to current version): none
** This file is part of the CVC4 prototype.
** Copyright (c) 2009, 2010 The Analysis of Computer Systems Group (ACSys)
** Courant Institute of Mathematical Sciences
** New York University
** See the file COPYING in the top-level source directory for licensing
** information.\endverbatim
**
** \brief Base for theory interface.
**
** Base for theory interface.
**/
#include "theory/theory.h"
#include "util/Assert.h"
#include <vector>
using namespace std;
namespace CVC4 {
namespace theory {
Node Theory::get() {
Assert( !d_facts.empty(),
"Theory::get() called with assertion queue empty!" );
Node fact = d_facts.front();
d_facts.pop_front();
Debug("theory") << "Theory::get() => " << fact
<< "(" << d_facts.size() << " left)" << std::endl;
if(! fact.getAttribute(RegisteredAttr())) {
std::list<TNode> toReg;
toReg.push_back(fact);
Debug("theory") << "Theory::get(): registering new atom" << std::endl;
/* Essentially this is doing a breadth-first numbering of
* non-registered subterms with children. Any non-registered
* leaves are immediately registered. */
for(std::list<TNode>::iterator workp = toReg.begin();
workp != toReg.end();
++workp) {
TNode n = *workp;
if(n.hasOperator()) {
TNode c = n.getOperator();
if(! c.getAttribute(RegisteredAttr())) {
if(c.getNumChildren() == 0) {
c.setAttribute(RegisteredAttr(), true);
registerTerm(c);
} else {
toReg.push_back(c);
}
}
}
for(TNode::iterator i = n.begin(); i != n.end(); ++i) {
TNode c = *i;
if(! c.getAttribute(RegisteredAttr())) {
if(c.getNumChildren() == 0) {
c.setAttribute(RegisteredAttr(), true);
registerTerm(c);
} else {
toReg.push_back(c);
}
}
}
}
/* Now register the list of terms in reverse order. Between this
* and the above registration of leaves, this should ensure that
* all subterms in the entire tree were registered in
* reverse-topological order. */
for(std::list<TNode>::reverse_iterator i = toReg.rbegin();
i != toReg.rend();
++i) {
TNode n = *i;
/* Note that a shared TNode in the DAG rooted at "fact" could
* appear twice on the list, so we have to avoid hitting it
* twice. */
// FIXME when ExprSets are online, use one of those to avoid
// duplicates in the above?
if(! n.getAttribute(RegisteredAttr())) {
n.setAttribute(RegisteredAttr(), true);
registerTerm(n);
}
}
}
return fact;
}
std::ostream& operator<<(std::ostream& os, Theory::Effort level){
switch(level){
case Theory::MIN_EFFORT:
os << "MIN_EFFORT"; break;
case Theory::QUICK_CHECK:
os << "QUICK_CHECK:"; break;
case Theory::STANDARD:
os << "STANDARD"; break;
case Theory::FULL_EFFORT:
os << "FULL_EFFORT"; break;
default:
Unreachable();
}
return os;
}
}/* CVC4::theory namespace */
}/* CVC4 namespace */
|