From 7342d1ca87397f3d5beb2c04b819243303e69a7c Mon Sep 17 00:00:00 2001 From: Dejan Jovanović Date: Tue, 5 Jul 2011 16:21:50 +0000 Subject: updated preprocessing and rewriting input equalities into inequalities for LRA --- test/regress/regress0/preprocess/preprocess_02.cvc | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 test/regress/regress0/preprocess/preprocess_02.cvc (limited to 'test/regress/regress0/preprocess/preprocess_02.cvc') diff --git a/test/regress/regress0/preprocess/preprocess_02.cvc b/test/regress/regress0/preprocess/preprocess_02.cvc new file mode 100644 index 000000000..7907d87ec --- /dev/null +++ b/test/regress/regress0/preprocess/preprocess_02.cvc @@ -0,0 +1,10 @@ +% EXPECT: valid + +a0, a1, a2, a3, a4, a5, a6, a7, a8, a9: BOOLEAN; + +ASSERT (NOT a5); + +QUERY NOT (a0 AND a1 AND a2 AND a3 AND a4 AND a5 AND a6 AND a7 AND a8 AND a9); + +% EXIT: 20 + -- cgit v1.2.3