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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2018-02-15 17:34:54 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-02-15 17:34:54 -0600 |
| commit | 98b9a45b8659e318bc529c223717f9f2fcd3b503 (patch) | |
| tree | ff32335537cba701f0dd3f08cbed7fe880f25bc9 /test | |
| parent | 55037e0bcef45c795f28ff3fcf6c1055af465c70 (diff) | |
Fix corner case for rewrite of mult by pow 2 (#1601)
Diffstat (limited to 'test')
| -rw-r--r-- | test/regress/regress0/bv/Makefile.am | 3 | ||||
| -rw-r--r-- | test/regress/regress0/bv/mult-pow2-negative.smt2 | 5 |
2 files changed, 7 insertions, 1 deletions
diff --git a/test/regress/regress0/bv/Makefile.am b/test/regress/regress0/bv/Makefile.am index 44691d1e2..eeeff7391 100644 --- a/test/regress/regress0/bv/Makefile.am +++ b/test/regress/regress0/bv/Makefile.am @@ -101,7 +101,8 @@ SMT_TESTS = \ divtest_2_6.smt2 \ mul-neg-unsat.smt2 \ mul-negpow2.smt2 \ - bvmul-pow2-only.smt2 + bvmul-pow2-only.smt2 \ + mult-pow2-negative.smt2 # Regression tests for PL inputs CVC_TESTS = bvsimple.cvc sizecheck.cvc diff --git a/test/regress/regress0/bv/mult-pow2-negative.smt2 b/test/regress/regress0/bv/mult-pow2-negative.smt2 new file mode 100644 index 000000000..2f1697dbf --- /dev/null +++ b/test/regress/regress0/bv/mult-pow2-negative.smt2 @@ -0,0 +1,5 @@ +(set-logic QF_BV) +(set-info :status sat) +(declare-fun x () (_ BitVec 4)) +(assert (not (= (bvmul (bvneg (bvmul #b1111 #b1111)) #b1111) x))) +(check-sat) |