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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2018-01-12 16:05:52 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-01-12 16:05:52 -0600 |
| commit | 17820d7e0606b19e22dc082b2f438b323ac49ff8 (patch) | |
| tree | edfa0f4c971f7427b3b04f1b3553944716af8e73 /test/regress | |
| parent | 51d2682c44761e0b3a30e75188b390b791d5dd48 (diff) | |
Improvements for CBQI BV (#1504)
Diffstat (limited to 'test/regress')
| -rw-r--r-- | test/regress/regress0/sygus/Base16_1.sy | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/regress/regress0/sygus/Base16_1.sy b/test/regress/regress0/sygus/Base16_1.sy index 5833751cb..b54c7688b 100644 --- a/test/regress/regress0/sygus/Base16_1.sy +++ b/test/regress/regress0/sygus/Base16_1.sy @@ -1,5 +1,5 @@ ; EXPECT: unsat -; COMMAND-LINE: --sygus-qe-preproc --cbqi-bv-rm-extract --sygus-out=status --cbqi-bv --cegqi-si=all +; COMMAND-LINE: --sygus-qe-preproc --cbqi-full --sygus-out=status --cegqi-si=all (set-logic BV) (define-fun B ((h (BitVec 8)) (l (BitVec 8)) (v (BitVec 8))) (BitVec 8) (bvlshr (bvshl v (bvsub #x07 h)) (bvsub #x07 (bvsub h l)))) |