diff options
| author | Mathias Preiner <mathias.preiner@gmail.com> | 2021-03-05 16:17:15 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-06 00:17:15 +0000 |
| commit | c6fffe4fd328401f7f7e0757303e8dea5f6c14a4 (patch) | |
| tree | 84bbb3f44fa7ffbeba0c0baf9b7b22f036d2e9f4 /test/regress | |
| parent | 555e4b0b6b10e9170676c0a3ef9b778322f3327f (diff) | |
Remove SMT-LIB 2.5 and 2.0 support. (#6068)
This commit removes parser and printer support for old SMT-LIB standards and also converts all regression tests to 2.6.
Diffstat (limited to 'test/regress')
210 files changed, 275 insertions, 354 deletions
diff --git a/test/regress/CMakeLists.txt b/test/regress/CMakeLists.txt index 8da7cfb05..140978d3d 100644 --- a/test/regress/CMakeLists.txt +++ b/test/regress/CMakeLists.txt @@ -542,7 +542,6 @@ set(regress_0_tests regress0/fmf/Arrow_Order-smtlib.778341.smtv1.smt2 regress0/fmf/bounded_sets.smt2 regress0/fmf/bug-041417-set-options.cvc - regress0/fmf/bug652.smt2 regress0/fmf/bug782.smt2 regress0/fmf/cruanes-no-minimal-unk.smt2 regress0/fmf/fc-simple.smt2 @@ -645,7 +644,6 @@ set(regress_0_tests regress0/ite2.smt2 regress0/ite3.smt2 regress0/ite4.smt2 - regress0/lang_opts_2_5.smt2 regress0/lang_opts_2_6_1.smt2 regress0/lemmas/clocksynchro_5clocks.main_invar.base.model.smtv1.smt2 regress0/lemmas/fs_not_sc_seen.induction.smtv1.smt2 diff --git a/test/regress/regress0/arith/bug569.smt2 b/test/regress/regress0/arith/bug569.smt2 index e1ca49ac5..c9a84d1ec 100644 --- a/test/regress/regress0/arith/bug569.smt2 +++ b/test/regress/regress0/arith/bug569.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --no-check-unsat-cores ; EXPECT: unsat (set-logic QF_AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/arith/div.01.smt2 b/test/regress/regress0/arith/div.01.smt2 index d7d587021..7330790f8 100644 --- a/test/regress/regress0/arith/div.01.smt2 +++ b/test/regress/regress0/arith/div.01.smt2 @@ -1,5 +1,5 @@ (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun n () Int) diff --git a/test/regress/regress0/arith/div.02.smt2 b/test/regress/regress0/arith/div.02.smt2 index 37dfcbbc1..4706c2a55 100644 --- a/test/regress/regress0/arith/div.02.smt2 +++ b/test/regress/regress0/arith/div.02.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: -q ; EXPECT: sat (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun n () Int) diff --git a/test/regress/regress0/arith/div.04.smt2 b/test/regress/regress0/arith/div.04.smt2 index c30b1cd2f..19124d3fc 100644 --- a/test/regress/regress0/arith/div.04.smt2 +++ b/test/regress/regress0/arith/div.04.smt2 @@ -1,5 +1,5 @@ (set-logic QF_NRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun x () Real) (declare-fun y () Real) diff --git a/test/regress/regress0/arith/div.05.smt2 b/test/regress/regress0/arith/div.05.smt2 index fd3e4ae48..99e6b04d5 100644 --- a/test/regress/regress0/arith/div.05.smt2 +++ b/test/regress/regress0/arith/div.05.smt2 @@ -1,6 +1,6 @@ ; EXPECT: sat (set-logic QF_NRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun x () Real) (declare-fun y () Real) diff --git a/test/regress/regress0/arith/div.07.smt2 b/test/regress/regress0/arith/div.07.smt2 index 4c45b32c8..5f1fcb060 100644 --- a/test/regress/regress0/arith/div.07.smt2 +++ b/test/regress/regress0/arith/div.07.smt2 @@ -1,5 +1,5 @@ (set-logic QF_NRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun x () Real) (declare-fun y () Real) diff --git a/test/regress/regress0/arith/integers/ackermann4.smt2 b/test/regress/regress0/arith/integers/ackermann4.smt2 index 34aa56480..bf55b41c2 100644 --- a/test/regress/regress0/arith/integers/ackermann4.smt2 +++ b/test/regress/regress0/arith/integers/ackermann4.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --ackermann --no-check-models --no-check-unsat-cores ; EXPECT: unsat (set-logic QF_ALIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) diff --git a/test/regress/regress0/arith/integers/ackermann5.smt2 b/test/regress/regress0/arith/integers/ackermann5.smt2 index debd29344..8d6f124cd 100644 --- a/test/regress/regress0/arith/integers/ackermann5.smt2 +++ b/test/regress/regress0/arith/integers/ackermann5.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --ackermann --no-check-models ; EXPECT: sat (set-logic QF_UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (declare-fun v0 () Int) (declare-fun f (Int) Int) diff --git a/test/regress/regress0/arith/integers/ackermann6.smt2 b/test/regress/regress0/arith/integers/ackermann6.smt2 index 78f5a3658..96bf54703 100644 --- a/test/regress/regress0/arith/integers/ackermann6.smt2 +++ b/test/regress/regress0/arith/integers/ackermann6.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --ackermann --no-check-models --no-check-unsat-cores ; EXPECT: unsat (set-logic QF_UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (declare-fun v0 () Int) (declare-fun f (Int) Int) diff --git a/test/regress/regress0/arith/mod.01.smt2 b/test/regress/regress0/arith/mod.01.smt2 index 3a6d9a3d3..c83954628 100644 --- a/test/regress/regress0/arith/mod.01.smt2 +++ b/test/regress/regress0/arith/mod.01.smt2 @@ -1,6 +1,6 @@ ; EXPECT: sat (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun n () Int) (declare-fun x () Int) diff --git a/test/regress/regress0/arith/mult.01.smt2 b/test/regress/regress0/arith/mult.01.smt2 index 4e2956d9d..8042e3cab 100644 --- a/test/regress/regress0/arith/mult.01.smt2 +++ b/test/regress/regress0/arith/mult.01.smt2 @@ -1,6 +1,6 @@ ; EXPECT: unsat (set-logic QF_NRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun n () Real) (declare-fun x () Real) diff --git a/test/regress/regress0/arrays/arrays0.smt2 b/test/regress/regress0/arrays/arrays0.smt2 index 652ff0bcb..ffc7d3e8f 100644 --- a/test/regress/regress0/arrays/arrays0.smt2 +++ b/test/regress/regress0/arrays/arrays0.smt2 @@ -8,7 +8,7 @@ http://www.ai.dist.unige.it/pdpar05/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Index 0) diff --git a/test/regress/regress0/arrays/arrays1.smt2 b/test/regress/regress0/arrays/arrays1.smt2 index f001cc33e..6f6773916 100644 --- a/test/regress/regress0/arrays/arrays1.smt2 +++ b/test/regress/regress0/arrays/arrays1.smt2 @@ -8,7 +8,7 @@ http://www.ai.dist.unige.it/pdpar05/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Index 0) diff --git a/test/regress/regress0/arrays/arrays2.smt2 b/test/regress/regress0/arrays/arrays2.smt2 index 7c14477e2..7e89ad6b2 100644 --- a/test/regress/regress0/arrays/arrays2.smt2 +++ b/test/regress/regress0/arrays/arrays2.smt2 @@ -8,7 +8,7 @@ http://www.ai.dist.unige.it/pdpar05/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-sort Index 0) diff --git a/test/regress/regress0/arrays/arrays3.smt2 b/test/regress/regress0/arrays/arrays3.smt2 index a21397b1d..aecfeee08 100644 --- a/test/regress/regress0/arrays/arrays3.smt2 +++ b/test/regress/regress0/arrays/arrays3.smt2 @@ -8,7 +8,7 @@ http://www.ai.dist.unige.it/pdpar05/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-sort Index 0) diff --git a/test/regress/regress0/arrays/arrays4.smt2 b/test/regress/regress0/arrays/arrays4.smt2 index f4afded65..e9acd5304 100644 --- a/test/regress/regress0/arrays/arrays4.smt2 +++ b/test/regress/regress0/arrays/arrays4.smt2 @@ -8,7 +8,7 @@ http://www.ai.dist.unige.it/pdpar05/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Index 0) diff --git a/test/regress/regress0/aufbv/bug580.delta.smt2 b/test/regress/regress0/aufbv/bug580.delta.smt2 index bc9a66f9c..b06be7ea7 100644 --- a/test/regress/regress0/aufbv/bug580.delta.smt2 +++ b/test/regress/regress0/aufbv/bug580.delta.smt2 @@ -1,5 +1,5 @@ (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_AUFBV) diff --git a/test/regress/regress0/auflia/bug336.smt2 b/test/regress/regress0/auflia/bug336.smt2 index f8909c23c..34af91c6c 100644 --- a/test/regress/regress0/auflia/bug336.smt2 +++ b/test/regress/regress0/auflia/bug336.smt2 @@ -2,7 +2,7 @@ (set-info :source | This is based on an example in Section 6.2 of "A Decision Procedure for an Extensional Theory of Arrays" by Stump, Barrett, Dill, and Levitt. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "check") (set-info :status unsat) (set-info :notes |This benchmark is designed to require an array DP to propagate a properly entailed disjunction of equalities between shared terms.|) diff --git a/test/regress/regress0/bt-test-00.smt2 b/test/regress/regress0/bt-test-00.smt2 index 517806542..167fb6323 100644 --- a/test/regress/regress0/bt-test-00.smt2 +++ b/test/regress/regress0/bt-test-00.smt2 @@ -1,6 +1,6 @@ ; EXPECT: unsat (set-logic QF_UF) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) diff --git a/test/regress/regress0/bt-test-01.smt2 b/test/regress/regress0/bt-test-01.smt2 index e17bd2d7a..0b2b8b9f9 100644 --- a/test/regress/regress0/bt-test-01.smt2 +++ b/test/regress/regress0/bt-test-01.smt2 @@ -1,6 +1,6 @@ ; EXPECT: unsat (set-logic QF_UF) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) diff --git a/test/regress/regress0/bug365.smt2 b/test/regress/regress0/bug365.smt2 index 6dd48a849..9c9ac8244 100644 --- a/test/regress/regress0/bug365.smt2 +++ b/test/regress/regress0/bug365.smt2 @@ -1,5 +1,5 @@ (set-logic QF_LIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (assert (let ((a 2)) diff --git a/test/regress/regress0/bug578.smt2 b/test/regress/regress0/bug578.smt2 index a4d53f8bf..f0e204310 100644 --- a/test/regress/regress0/bug578.smt2 +++ b/test/regress/regress0/bug578.smt2 @@ -1,4 +1,4 @@ -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (set-logic QF_BV) (declare-fun v0 () (_ BitVec 1)) diff --git a/test/regress/regress0/buggy-ite.smt2 b/test/regress/regress0/buggy-ite.smt2 index 79e91b55e..5eac7700f 100644 --- a/test/regress/regress0/buggy-ite.smt2 +++ b/test/regress/regress0/buggy-ite.smt2 @@ -2,7 +2,7 @@ ; removal for PARAMETERIZED kinds. ; Thanks to Andrew Reynolds for catching this. (set-logic QF_UF) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-sort U 0) (declare-fun a () U) diff --git a/test/regress/regress0/bv/ackermann1.smt2 b/test/regress/regress0/bv/ackermann1.smt2 index bdf74ce49..fa1963322 100644 --- a/test/regress/regress0/bv/ackermann1.smt2 +++ b/test/regress/regress0/bv/ackermann1.smt2 @@ -2,7 +2,7 @@ ; COMMAND-LINE: --bitblast=eager --bv-solver=simple --no-check-models --no-check-unsat-cores ; EXPECT: sat (set-logic QF_UFBV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (declare-fun v0 () (_ BitVec 4)) (declare-fun f ((_ BitVec 4)) (_ BitVec 4)) diff --git a/test/regress/regress0/bv/ackermann2.smt2 b/test/regress/regress0/bv/ackermann2.smt2 index 518faf597..80b8126a0 100644 --- a/test/regress/regress0/bv/ackermann2.smt2 +++ b/test/regress/regress0/bv/ackermann2.smt2 @@ -4,7 +4,7 @@ ; COMMAND-LINE: --bitblast=eager --bv-sat-solver=cryptominisat --no-check-unsat-cores ; EXPECT: unsat (set-logic QF_UFBV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v0 () (_ BitVec 4)) diff --git a/test/regress/regress0/bv/ackermann3.smt2 b/test/regress/regress0/bv/ackermann3.smt2 index ec3efeedd..9b44b8d63 100644 --- a/test/regress/regress0/bv/ackermann3.smt2 +++ b/test/regress/regress0/bv/ackermann3.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --bitblast=eager --no-check-models --no-check-unsat-cores ; EXPECT: unsat (set-logic QF_ABV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) diff --git a/test/regress/regress0/bv/ackermann4.smt2 b/test/regress/regress0/bv/ackermann4.smt2 index 05ffef452..69bf76937 100644 --- a/test/regress/regress0/bv/ackermann4.smt2 +++ b/test/regress/regress0/bv/ackermann4.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --bitblast=eager --no-check-models --no-check-unsat-cores ; EXPECT: sat (set-logic QF_UFBV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (declare-fun v0 () (_ BitVec 4)) (declare-fun f ((_ BitVec 4)) (_ BitVec 4)) diff --git a/test/regress/regress0/bv/bv-options4.smt2 b/test/regress/regress0/bv/bv-options4.smt2 index b7a78e3b5..f804f1133 100644 --- a/test/regress/regress0/bv/bv-options4.smt2 +++ b/test/regress/regress0/bv/bv-options4.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat ; EXIT: 0 (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (declare-fun v0 () (_ BitVec 16)) (declare-fun v1 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/core/constant_core.smt2 b/test/regress/regress0/bv/core/constant_core.smt2 index 1e2bcde68..a353a5c6f 100644 --- a/test/regress/regress0/bv/core/constant_core.smt2 +++ b/test/regress/regress0/bv/core/constant_core.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x () (_ BitVec 3)) diff --git a/test/regress/regress0/bv/inequality00.smt2 b/test/regress/regress0/bv/inequality00.smt2 index dc6285d52..c95b7caa6 100644 --- a/test/regress/regress0/bv/inequality00.smt2 +++ b/test/regress/regress0/bv/inequality00.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/inequality01.smt2 b/test/regress/regress0/bv/inequality01.smt2 index 73a2515df..f094d0d11 100644 --- a/test/regress/regress0/bv/inequality01.smt2 +++ b/test/regress/regress0/bv/inequality01.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/inequality02.smt2 b/test/regress/regress0/bv/inequality02.smt2 index 05f11311f..75ecc47f4 100644 --- a/test/regress/regress0/bv/inequality02.smt2 +++ b/test/regress/regress0/bv/inequality02.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/inequality03.smt2 b/test/regress/regress0/bv/inequality03.smt2 index a47551d14..d69b978f7 100644 --- a/test/regress/regress0/bv/inequality03.smt2 +++ b/test/regress/regress0/bv/inequality03.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/inequality04.smt2 b/test/regress/regress0/bv/inequality04.smt2 index 35607eaef..dc02322b1 100644 --- a/test/regress/regress0/bv/inequality04.smt2 +++ b/test/regress/regress0/bv/inequality04.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/bv/inequality05.smt2 b/test/regress/regress0/bv/inequality05.smt2 index d8cf9cf99..df9f5a23a 100644 --- a/test/regress/regress0/bv/inequality05.smt2 +++ b/test/regress/regress0/bv/inequality05.smt2 @@ -1,5 +1,5 @@ (set-logic QF_BV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v0 () (_ BitVec 16)) diff --git a/test/regress/regress0/decision/quant-ex1.smt2 b/test/regress/regress0/decision/quant-ex1.smt2 index 749b0e218..3bb3d5999 100644 --- a/test/regress/regress0/decision/quant-ex1.smt2 +++ b/test/regress/regress0/decision/quant-ex1.smt2 @@ -2,7 +2,7 @@ ; EXPECT: sat (set-logic AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-sort U 0) diff --git a/test/regress/regress0/fmf/bug652.smt2 b/test/regress/regress0/fmf/bug652.smt2 deleted file mode 100644 index 13748eeea..000000000 --- a/test/regress/regress0/fmf/bug652.smt2 +++ /dev/null @@ -1,22 +0,0 @@ -; COMMAND-LINE: --fmf-fun --no-check-models -; EXPECT: sat -(set-logic UFDTSLIA) -(set-info :smt-lib-version 2.5) -(set-option :produce-models true) - -(declare-datatypes () ( - (List_boolean (List_boolean$CNil_boolean) (List_boolean$Cstr_boolean (List_boolean$Cstr_boolean$head Bool) (List_boolean$Cstr_boolean$tail List_boolean))) -) ) - -(define-funs-rec - ( - (f4208$lengthList_boolean((x List_boolean)) Int) - ) - ( - (ite (is-List_boolean$CNil_boolean x) 0 (+ 1 (f4208$lengthList_boolean (List_boolean$Cstr_boolean$tail x)))) - ) -) - - -(declare-const boolean Bool) -(check-sat) diff --git a/test/regress/regress0/fp/down-cast-RNA.smt2 b/test/regress/regress0/fp/down-cast-RNA.smt2 index 9509259a4..dc99ff144 100644 --- a/test/regress/regress0/fp/down-cast-RNA.smt2 +++ b/test/regress/regress0/fp/down-cast-RNA.smt2 @@ -4,7 +4,7 @@ (set-logic QF_FP) (set-info :source |Written by Andres Noetzli for issue #2183|) -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-info :category crafted) (set-info :status unsat) diff --git a/test/regress/regress0/fp/rti_3_5_bug.smt2 b/test/regress/regress0/fp/rti_3_5_bug.smt2 index 56c11bbf5..2c837b415 100644 --- a/test/regress/regress0/fp/rti_3_5_bug.smt2 +++ b/test/regress/regress0/fp/rti_3_5_bug.smt2 @@ -4,7 +4,7 @@ (set-logic QF_FP)
(set-info :source |Written by Martin for issue #2932|)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-info :category crafted)
(set-info :status unsat)
diff --git a/test/regress/regress0/get-value-incremental.smt2 b/test/regress/regress0/get-value-incremental.smt2 index c45cced82..6c3ee89ab 100644 --- a/test/regress/regress0/get-value-incremental.smt2 +++ b/test/regress/regress0/get-value-incremental.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --incremental ; EXPECT: sat ; EXPECT: (((f 0) 1)) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic QF_UFLIA) diff --git a/test/regress/regress0/get-value-ints.smt2 b/test/regress/regress0/get-value-ints.smt2 index 97d8d1176..5434e3746 100644 --- a/test/regress/regress0/get-value-ints.smt2 +++ b/test/regress/regress0/get-value-ints.smt2 @@ -1,6 +1,6 @@ ; EXPECT: sat ; EXPECT: ((pos 1) (zero 0) (neg (- 6))) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic QF_LIA) diff --git a/test/regress/regress0/get-value-reals-ints.smt2 b/test/regress/regress0/get-value-reals-ints.smt2 index e155255e7..8951cc797 100644 --- a/test/regress/regress0/get-value-reals-ints.smt2 +++ b/test/regress/regress0/get-value-reals-ints.smt2 @@ -1,6 +1,6 @@ ; EXPECT: sat ; EXPECT: ((pos_int 5) (pos_real_int_value 3.0) (pos_rat (/ 1 3)) (zero 0.0) (neg_rat (/ (- 2) 3)) (neg_real_int_value (- 2.0)) (neg_int (- 6))) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic QF_LIRA) diff --git a/test/regress/regress0/get-value-reals.smt2 b/test/regress/regress0/get-value-reals.smt2 index 5d5319955..553c5ed72 100644 --- a/test/regress/regress0/get-value-reals.smt2 +++ b/test/regress/regress0/get-value-reals.smt2 @@ -1,6 +1,6 @@ ; EXPECT: sat ; EXPECT: ((pos_int 3.0) (pos_rat (/ 1 3)) (zero 0.0) (neg_rat (/ (- 2) 3)) (neg_int (- 2.0))) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic QF_LRA) diff --git a/test/regress/regress0/hung10_itesdk_output1.smt2 b/test/regress/regress0/hung10_itesdk_output1.smt2 index 8bcdfdfbc..2dcbf1fcd 100644 --- a/test/regress/regress0/hung10_itesdk_output1.smt2 +++ b/test/regress/regress0/hung10_itesdk_output1.smt2 @@ -1,6 +1,6 @@ ( set-logic QF_ALL_SUPPORTED) ( set-info :source | SMT-COMP'06 organizers |) -( set-info :smt-lib-version 2.0) +( set-info :smt-lib-version 2.6) ( set-info :category "check") ( set-info :status sat) ( declare-fun x1 () Bool) diff --git a/test/regress/regress0/hung13sdk_output1.smt2 b/test/regress/regress0/hung13sdk_output1.smt2 index bf3ab9a26..7886153b0 100644 --- a/test/regress/regress0/hung13sdk_output1.smt2 +++ b/test/regress/regress0/hung13sdk_output1.smt2 @@ -1,6 +1,6 @@ ( set-logic QF_ALL_SUPPORTED) ( set-info :source | SMT-COMP'06 organizers |) -( set-info :smt-lib-version 2.0) +( set-info :smt-lib-version 2.6) ( set-info :category "check") ( set-info :status sat) ( declare-fun x1 () Bool) diff --git a/test/regress/regress0/lang_opts_2_5.smt2 b/test/regress/regress0/lang_opts_2_5.smt2 deleted file mode 100644 index 5a56960f0..000000000 --- a/test/regress/regress0/lang_opts_2_5.smt2 +++ /dev/null @@ -1,7 +0,0 @@ -; Check that the language set in the command line options has higher priority -; than the language specified in the input file. -; -; COMMAND-LINE: --lang=smt2.5 -; EXPECT: "LANG_SMTLIB_V2_5" -(set-info :smt-lib-version 2.6) -(get-option :input-language) diff --git a/test/regress/regress0/nl/magnitude-wrong-1020-m.smt2 b/test/regress/regress0/nl/magnitude-wrong-1020-m.smt2 index 9411224e5..6575385d5 100644 --- a/test/regress/regress0/nl/magnitude-wrong-1020-m.smt2 +++ b/test/regress/regress0/nl/magnitude-wrong-1020-m.smt2 @@ -7,7 +7,7 @@ From termination analysis of term rewriting. Submitted by Harald Roman Zankl <Harald.Zankl@uibk.ac.at> |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (define-fun x6 () Real diff --git a/test/regress/regress0/nl/very-easy-sat.smt2 b/test/regress/regress0/nl/very-easy-sat.smt2 index 06efa5806..0a0405a8e 100644 --- a/test/regress/regress0/nl/very-easy-sat.smt2 +++ b/test/regress/regress0/nl/very-easy-sat.smt2 @@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun skoC () Real) diff --git a/test/regress/regress0/nl/very-simple-unsat.smt2 b/test/regress/regress0/nl/very-simple-unsat.smt2 index e23d2d542..839fbb88b 100644 --- a/test/regress/regress0/nl/very-simple-unsat.smt2 +++ b/test/regress/regress0/nl/very-simple-unsat.smt2 @@ -5,7 +5,7 @@ Harald Roman Zankl <Harald.Zankl@uibk.ac.at> |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun a () Real) diff --git a/test/regress/regress0/parser/as.smt2 b/test/regress/regress0/parser/as.smt2 index 2ba689541..2dc5c0e45 100644 --- a/test/regress/regress0/parser/as.smt2 +++ b/test/regress/regress0/parser/as.smt2 @@ -1,5 +1,5 @@ (set-logic QF_UF) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-sort I 0) diff --git a/test/regress/regress0/parser/strings20.smt2 b/test/regress/regress0/parser/strings20.smt2 index 3682e06e6..48e1113ea 100644 --- a/test/regress/regress0/parser/strings20.smt2 +++ b/test/regress/regress0/parser/strings20.smt2 @@ -1,15 +1,15 @@ ; EXPECT: sat ; EXPECT: ( -; EXPECT: (define-fun s () String "\"") +; EXPECT: (define-fun s () String "\u{5c}""") ; EXPECT: ) (set-logic QF_S) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (declare-fun s () String) -(assert (= s "\"")) +(assert (= s "\""")) (check-sat) (get-model) diff --git a/test/regress/regress0/parser/strings25.smt2 b/test/regress/regress0/parser/strings25.smt2 index f8cc084e6..eac95dd5c 100644 --- a/test/regress/regress0/parser/strings25.smt2 +++ b/test/regress/regress0/parser/strings25.smt2 @@ -4,7 +4,6 @@ ; EXPECT: ) (set-logic QF_S) -(set-info :smt-lib-version 2.5) (set-option :produce-models true) (declare-fun s () String) diff --git a/test/regress/regress0/push-pop/bug691.smt2 b/test/regress/regress0/push-pop/bug691.smt2 index df8964658..dd4e9ea09 100644 --- a/test/regress/regress0/push-pop/bug691.smt2 +++ b/test/regress/regress0/push-pop/bug691.smt2 @@ -2,12 +2,9 @@ ; EXPECT: sat ; EXPECT: sat (set-logic UFDTSLIA) -(set-info :smt-lib-version 2.5) - -(declare-datatypes () ( - (Response (Response$Response (Response$Response$success Bool))) - ) ) +(set-info :smt-lib-version 2.6) +(declare-datatype Response ((Response$Response (Response$Response$success Bool)))) (push 1) (declare-fun $BLout$3248$0$1$() Response) diff --git a/test/regress/regress0/quantifiers/bug290.smt2 b/test/regress/regress0/quantifiers/bug290.smt2 index 650d6aab0..fb2955eb0 100644 --- a/test/regress/regress0/quantifiers/bug290.smt2 +++ b/test/regress/regress0/quantifiers/bug290.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Simple list theorem |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort List 0) diff --git a/test/regress/regress0/quantifiers/bug291.smt2 b/test/regress/regress0/quantifiers/bug291.smt2 index 959d83c7f..c8e3111c8 100644 --- a/test/regress/regress0/quantifiers/bug291.smt2 +++ b/test/regress/regress0/quantifiers/bug291.smt2 @@ -5,7 +5,7 @@ Boogie/Spec# benchmarks. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun select2 (Int) Int) diff --git a/test/regress/regress0/quantifiers/ex3.smt2 b/test/regress/regress0/quantifiers/ex3.smt2 index fd887b4bc..c08908e30 100644 --- a/test/regress/regress0/quantifiers/ex3.smt2 +++ b/test/regress/regress0/quantifiers/ex3.smt2 @@ -1,5 +1,5 @@ (set-logic AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort U 0) diff --git a/test/regress/regress0/quantifiers/ex6.smt2 b/test/regress/regress0/quantifiers/ex6.smt2 index 7285e1c4f..294869277 100644 --- a/test/regress/regress0/quantifiers/ex6.smt2 +++ b/test/regress/regress0/quantifiers/ex6.smt2 @@ -1,5 +1,5 @@ (set-logic AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort U 0) diff --git a/test/regress/regress0/strings/bug001.smt2 b/test/regress/regress0/strings/bug001.smt2 index a8d2d8992..751cacd8f 100644 --- a/test/regress/regress0/strings/bug001.smt2 +++ b/test/regress/regress0/strings/bug001.smt2 @@ -1,4 +1,4 @@ -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-logic QF_S) (set-info :status sat) @@ -6,10 +6,10 @@ (declare-fun y () String) (declare-fun z () String) -(assert (= "\x4a" x)) -(assert (= "\x6a" y)) +(assert (= "J" x)) +(assert (= "j" y)) -(assert (= "\x4A" z)) +(assert (= "J" z)) (assert (= x z)) diff --git a/test/regress/regress0/strings/bug002.smt2 b/test/regress/regress0/strings/bug002.smt2 index 5bf21ebb9..f35a5fffb 100644 --- a/test/regress/regress0/strings/bug002.smt2 +++ b/test/regress/regress0/strings/bug002.smt2 @@ -1,10 +1,10 @@ -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-logic ASLIA) (set-option :strings-exp true) (set-info :status sat) ; regex = [\*-,\t\*-\|](.{6,}()?)+ -(define-fun strinre ((?s String)) Bool (str.in.re ?s (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") (re.union re.nostr (re.range "*" ",") (str.to.re "\t") (re.range "*" "|") ) (re.+ (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") ((_ re.^ 6) re.allchar) (re.opt (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") ) ) ) ) ) ) ) ) ) ) +(define-fun strinre ((?s String)) Bool (str.in_re ?s (re.union re.none (re.++ (str.to_re "") (str.to_re "") (re.union re.none (re.range "*" ",") (str.to_re "\t") (re.range "*" "|") ) (re.+ (re.union re.none (re.++ (str.to_re "") (str.to_re "") ((_ re.^ 6) re.allchar) (re.opt (re.union re.none (re.++ (str.to_re "") (str.to_re "") ) ) ) ) ) ) ) ) ) ) (assert (not (strinre "6O\1\127\n?"))) (check-sat) diff --git a/test/regress/regress0/strings/escchar.smt2 b/test/regress/regress0/strings/escchar.smt2 index 67a184ade..a8a7c242f 100644 --- a/test/regress/regress0/strings/escchar.smt2 +++ b/test/regress/regress0/strings/escchar.smt2 @@ -1,11 +1,11 @@ (set-logic QF_S) (set-info :status sat) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (declare-fun x () String) (declare-const I Int) -(assert (= x "\0\1\2\3\04\005\x06\7\8\9ABC\\\"\t\a\b")) +(assert (= x "\0\1\2\3\04\005\x06\7\8\9ABC\\""\t\a\b")) (assert (= I (str.len x))) diff --git a/test/regress/regress0/uflia/check01.smt2 b/test/regress/regress0/uflia/check01.smt2 index 33be9346a..f182c5fbe 100644 --- a/test/regress/regress0/uflia/check01.smt2 +++ b/test/regress/regress0/uflia/check01.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --incremental ; EXPECT: sat (set-logic QF_UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun f (Int) Bool) diff --git a/test/regress/regress0/unconstrained/arith.smt2 b/test/regress/regress0/unconstrained/arith.smt2 index 3dfab3b0e..fd951c7ab 100644 --- a/test/regress/regress0/unconstrained/arith.smt2 +++ b/test/regress/regress0/unconstrained/arith.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/arith2.smt2 b/test/regress/regress0/unconstrained/arith2.smt2 index d6206287a..bf9f34298 100644 --- a/test/regress/regress0/unconstrained/arith2.smt2 +++ b/test/regress/regress0/unconstrained/arith2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/arith3.smt2 b/test/regress/regress0/unconstrained/arith3.smt2 index fd24c3f65..edf0d4cdf 100644 --- a/test/regress/regress0/unconstrained/arith3.smt2 +++ b/test/regress/regress0/unconstrained/arith3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/arith4.smt2 b/test/regress/regress0/unconstrained/arith4.smt2 index 507a18a78..f68ebf88a 100644 --- a/test/regress/regress0/unconstrained/arith4.smt2 +++ b/test/regress/regress0/unconstrained/arith4.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFNIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/arith5.smt2 b/test/regress/regress0/unconstrained/arith5.smt2 index 5e54083a5..cc19b5389 100644 --- a/test/regress/regress0/unconstrained/arith5.smt2 +++ b/test/regress/regress0/unconstrained/arith5.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Real) diff --git a/test/regress/regress0/unconstrained/arith6.smt2 b/test/regress/regress0/unconstrained/arith6.smt2 index ce3630264..24e57b0f7 100644 --- a/test/regress/regress0/unconstrained/arith6.smt2 +++ b/test/regress/regress0/unconstrained/arith6.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Real) diff --git a/test/regress/regress0/unconstrained/arith7.smt2 b/test/regress/regress0/unconstrained/arith7.smt2 index 105320632..5fe061803 100644 --- a/test/regress/regress0/unconstrained/arith7.smt2 +++ b/test/regress/regress0/unconstrained/arith7.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFLIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/array1.smt2 b/test/regress/regress0/unconstrained/array1.smt2 index f1acfa759..5c8ff5147 100644 --- a/test/regress/regress0/unconstrained/array1.smt2 +++ b/test/regress/regress0/unconstrained/array1.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBV) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () (_ BitVec 16)) diff --git a/test/regress/regress0/unconstrained/bvbool.smt2 b/test/regress/regress0/unconstrained/bvbool.smt2 index b1943124e..9964aa728 100644 --- a/test/regress/regress0/unconstrained/bvbool.smt2 +++ b/test/regress/regress0/unconstrained/bvbool.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvbool2.smt2 b/test/regress/regress0/unconstrained/bvbool2.smt2 index 49b7d5fc8..788a0578b 100644 --- a/test/regress/regress0/unconstrained/bvbool2.smt2 +++ b/test/regress/regress0/unconstrained/bvbool2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvbool3.smt2 b/test/regress/regress0/unconstrained/bvbool3.smt2 index f24b129e0..524fdd107 100644 --- a/test/regress/regress0/unconstrained/bvbool3.smt2 +++ b/test/regress/regress0/unconstrained/bvbool3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvcmp.smt2 b/test/regress/regress0/unconstrained/bvcmp.smt2 index ae50d350c..5a6c314bd 100644 --- a/test/regress/regress0/unconstrained/bvcmp.smt2 +++ b/test/regress/regress0/unconstrained/bvcmp.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () (_ BitVec 1)) diff --git a/test/regress/regress0/unconstrained/bvconcat.smt2 b/test/regress/regress0/unconstrained/bvconcat.smt2 index 6f4e38ec7..c93189837 100644 --- a/test/regress/regress0/unconstrained/bvconcat.smt2 +++ b/test/regress/regress0/unconstrained/bvconcat.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvconcat2.smt2 b/test/regress/regress0/unconstrained/bvconcat2.smt2 index 789e4c6c8..9e9ac87d3 100644 --- a/test/regress/regress0/unconstrained/bvconcat2.smt2 +++ b/test/regress/regress0/unconstrained/bvconcat2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvdiv.smt2 b/test/regress/regress0/unconstrained/bvdiv.smt2 index 990a8d457..2c2b4d5f8 100644 --- a/test/regress/regress0/unconstrained/bvdiv.smt2 +++ b/test/regress/regress0/unconstrained/bvdiv.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvext.smt2 b/test/regress/regress0/unconstrained/bvext.smt2 index b31efe3aa..dd4de7251 100644 --- a/test/regress/regress0/unconstrained/bvext.smt2 +++ b/test/regress/regress0/unconstrained/bvext.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvite.smt2 b/test/regress/regress0/unconstrained/bvite.smt2 index 3cac4670b..f89dd6b6b 100644 --- a/test/regress/regress0/unconstrained/bvite.smt2 +++ b/test/regress/regress0/unconstrained/bvite.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvmul.smt2 b/test/regress/regress0/unconstrained/bvmul.smt2 index a109d9471..c26304073 100644 --- a/test/regress/regress0/unconstrained/bvmul.smt2 +++ b/test/regress/regress0/unconstrained/bvmul.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvmul2.smt2 b/test/regress/regress0/unconstrained/bvmul2.smt2 index 4e413c24f..fd8cc1e3d 100644 --- a/test/regress/regress0/unconstrained/bvmul2.smt2 +++ b/test/regress/regress0/unconstrained/bvmul2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvmul3.smt2 b/test/regress/regress0/unconstrained/bvmul3.smt2 index 71cf37371..e38944082 100644 --- a/test/regress/regress0/unconstrained/bvmul3.smt2 +++ b/test/regress/regress0/unconstrained/bvmul3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvnot.smt2 b/test/regress/regress0/unconstrained/bvnot.smt2 index 4f62d2a0d..cdeb77a3b 100644 --- a/test/regress/regress0/unconstrained/bvnot.smt2 +++ b/test/regress/regress0/unconstrained/bvnot.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () (_ BitVec 1)) diff --git a/test/regress/regress0/unconstrained/bvsle.smt2 b/test/regress/regress0/unconstrained/bvsle.smt2 index 391a6c9d7..594ed0c4d 100644 --- a/test/regress/regress0/unconstrained/bvsle.smt2 +++ b/test/regress/regress0/unconstrained/bvsle.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvsle2.smt2 b/test/regress/regress0/unconstrained/bvsle2.smt2 index f23b119fe..fe4c4d4b4 100644 --- a/test/regress/regress0/unconstrained/bvsle2.smt2 +++ b/test/regress/regress0/unconstrained/bvsle2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvsle3.smt2 b/test/regress/regress0/unconstrained/bvsle3.smt2 index 2887cdca8..5d8359e31 100644 --- a/test/regress/regress0/unconstrained/bvsle3.smt2 +++ b/test/regress/regress0/unconstrained/bvsle3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvsle4.smt2 b/test/regress/regress0/unconstrained/bvsle4.smt2 index 289104ec8..0c60acfcb 100644 --- a/test/regress/regress0/unconstrained/bvsle4.smt2 +++ b/test/regress/regress0/unconstrained/bvsle4.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvsle5.smt2 b/test/regress/regress0/unconstrained/bvsle5.smt2 index cbe15db58..e8027465f 100644 --- a/test/regress/regress0/unconstrained/bvsle5.smt2 +++ b/test/regress/regress0/unconstrained/bvsle5.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvslt.smt2 b/test/regress/regress0/unconstrained/bvslt.smt2 index 2e20460c5..191038a4c 100644 --- a/test/regress/regress0/unconstrained/bvslt.smt2 +++ b/test/regress/regress0/unconstrained/bvslt.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvslt2.smt2 b/test/regress/regress0/unconstrained/bvslt2.smt2 index 743cfbebe..a22e51cc6 100644 --- a/test/regress/regress0/unconstrained/bvslt2.smt2 +++ b/test/regress/regress0/unconstrained/bvslt2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvslt3.smt2 b/test/regress/regress0/unconstrained/bvslt3.smt2 index db1f3dcd9..e702379ac 100644 --- a/test/regress/regress0/unconstrained/bvslt3.smt2 +++ b/test/regress/regress0/unconstrained/bvslt3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvslt4.smt2 b/test/regress/regress0/unconstrained/bvslt4.smt2 index 9c696d48b..bdda57a8d 100644 --- a/test/regress/regress0/unconstrained/bvslt4.smt2 +++ b/test/regress/regress0/unconstrained/bvslt4.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvslt5.smt2 b/test/regress/regress0/unconstrained/bvslt5.smt2 index c5696f0a2..2dbe3645c 100644 --- a/test/regress/regress0/unconstrained/bvslt5.smt2 +++ b/test/regress/regress0/unconstrained/bvslt5.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvule.smt2 b/test/regress/regress0/unconstrained/bvule.smt2 index d0678d87c..58e8f2796 100644 --- a/test/regress/regress0/unconstrained/bvule.smt2 +++ b/test/regress/regress0/unconstrained/bvule.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvule2.smt2 b/test/regress/regress0/unconstrained/bvule2.smt2 index 5dfa6c1b1..f3dd4860e 100644 --- a/test/regress/regress0/unconstrained/bvule2.smt2 +++ b/test/regress/regress0/unconstrained/bvule2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvule3.smt2 b/test/regress/regress0/unconstrained/bvule3.smt2 index e9892e598..e16baff02 100644 --- a/test/regress/regress0/unconstrained/bvule3.smt2 +++ b/test/regress/regress0/unconstrained/bvule3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvule4.smt2 b/test/regress/regress0/unconstrained/bvule4.smt2 index 0fccae301..564db9748 100644 --- a/test/regress/regress0/unconstrained/bvule4.smt2 +++ b/test/regress/regress0/unconstrained/bvule4.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvule5.smt2 b/test/regress/regress0/unconstrained/bvule5.smt2 index 4d4e0e95f..70ac8910f 100644 --- a/test/regress/regress0/unconstrained/bvule5.smt2 +++ b/test/regress/regress0/unconstrained/bvule5.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvult.smt2 b/test/regress/regress0/unconstrained/bvult.smt2 index 9429237a4..44bdefd62 100644 --- a/test/regress/regress0/unconstrained/bvult.smt2 +++ b/test/regress/regress0/unconstrained/bvult.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvult2.smt2 b/test/regress/regress0/unconstrained/bvult2.smt2 index c86699b48..f8eee92f6 100644 --- a/test/regress/regress0/unconstrained/bvult2.smt2 +++ b/test/regress/regress0/unconstrained/bvult2.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvult3.smt2 b/test/regress/regress0/unconstrained/bvult3.smt2 index ceb19ea75..43f79a569 100644 --- a/test/regress/regress0/unconstrained/bvult3.smt2 +++ b/test/regress/regress0/unconstrained/bvult3.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvult4.smt2 b/test/regress/regress0/unconstrained/bvult4.smt2 index 04008c006..fe716b139 100644 --- a/test/regress/regress0/unconstrained/bvult4.smt2 +++ b/test/regress/regress0/unconstrained/bvult4.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/bvult5.smt2 b/test/regress/regress0/unconstrained/bvult5.smt2 index 53f76f0d3..151db6f02 100644 --- a/test/regress/regress0/unconstrained/bvult5.smt2 +++ b/test/regress/regress0/unconstrained/bvult5.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress0/unconstrained/geq.smt2 b/test/regress/regress0/unconstrained/geq.smt2 index d3bcc506f..e84876133 100644 --- a/test/regress/regress0/unconstrained/geq.smt2 +++ b/test/regress/regress0/unconstrained/geq.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/gt.smt2 b/test/regress/regress0/unconstrained/gt.smt2 index d4d6d4a5d..2c118cd9c 100644 --- a/test/regress/regress0/unconstrained/gt.smt2 +++ b/test/regress/regress0/unconstrained/gt.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/leq.smt2 b/test/regress/regress0/unconstrained/leq.smt2 index 4eea4df9c..ed568c5fd 100644 --- a/test/regress/regress0/unconstrained/leq.smt2 +++ b/test/regress/regress0/unconstrained/leq.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/lt.smt2 b/test/regress/regress0/unconstrained/lt.smt2 index a0a42f4ef..06724ad45 100644 --- a/test/regress/regress0/unconstrained/lt.smt2 +++ b/test/regress/regress0/unconstrained/lt.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/uf1.smt2 b/test/regress/regress0/unconstrained/uf1.smt2 index 3e28c2f8b..f85054926 100644 --- a/test/regress/regress0/unconstrained/uf1.smt2 +++ b/test/regress/regress0/unconstrained/uf1.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun v1 () Int) diff --git a/test/regress/regress0/unconstrained/xor.smt2 b/test/regress/regress0/unconstrained/xor.smt2 index fcc66b015..cb0b39040 100644 --- a/test/regress/regress0/unconstrained/xor.smt2 +++ b/test/regress/regress0/unconstrained/xor.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --unconstrained-simp --no-check-models (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress1/arith/bug716.0.smt2 b/test/regress/regress1/arith/bug716.0.smt2 index dd2501bbb..9e05e8b3d 100644 --- a/test/regress/regress1/arith/bug716.0.smt2 +++ b/test/regress/regress1/arith/bug716.0.smt2 @@ -7,7 +7,7 @@ (set-logic AUFBVDTLIRA) ;; produced by cvc4_15.drv ;; (set-info :source |VC generated by SPARK 2014|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category industrial) (set-info :status unknown) ;;; generated by SMT-LIB2 driver diff --git a/test/regress/regress1/arith/div.03.smt2 b/test/regress/regress1/arith/div.03.smt2 index 8beef7a69..51568b706 100644 --- a/test/regress/regress1/arith/div.03.smt2 +++ b/test/regress/regress1/arith/div.03.smt2 @@ -1,6 +1,6 @@ ; EXPECT: unsat (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun x () Int) (declare-fun n () Int) diff --git a/test/regress/regress1/arith/div.06.smt2 b/test/regress/regress1/arith/div.06.smt2 index 45d687cab..b6a72d36f 100644 --- a/test/regress/regress1/arith/div.06.smt2 +++ b/test/regress/regress1/arith/div.06.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: -q ; EXPECT: sat (set-logic QF_NRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun x () Real) (declare-fun y () Real) diff --git a/test/regress/regress1/arith/div.08.smt2 b/test/regress/regress1/arith/div.08.smt2 index 0b0d73ac1..d43110947 100644 --- a/test/regress/regress1/arith/div.08.smt2 +++ b/test/regress/regress1/arith/div.08.smt2 @@ -1,5 +1,5 @@ (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun n () Int) diff --git a/test/regress/regress1/arith/mod.02.smt2 b/test/regress/regress1/arith/mod.02.smt2 index ee4333ea5..770de4c45 100644 --- a/test/regress/regress1/arith/mod.02.smt2 +++ b/test/regress/regress1/arith/mod.02.smt2 @@ -1,6 +1,6 @@ ; EXPECT: unsat (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-fun n () Int) diff --git a/test/regress/regress1/arith/mod.03.smt2 b/test/regress/regress1/arith/mod.03.smt2 index 583c72a93..58dbd2319 100644 --- a/test/regress/regress1/arith/mod.03.smt2 +++ b/test/regress/regress1/arith/mod.03.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: -q ; EXPECT: sat (set-logic QF_NIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun n () Int) (declare-fun x () Int) diff --git a/test/regress/regress1/arith/problem__003.smt2 b/test/regress/regress1/arith/problem__003.smt2 index 7af727e2a..fe177362c 100644 --- a/test/regress/regress1/arith/problem__003.smt2 +++ b/test/regress/regress1/arith/problem__003.smt2 @@ -3,7 +3,7 @@ Alberto Griggio |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (declare-fun x0 () Int) diff --git a/test/regress/regress1/aufbv/bug580.smt2 b/test/regress/regress1/aufbv/bug580.smt2 index 2f2074385..074c7523a 100644 --- a/test/regress/regress1/aufbv/bug580.smt2 +++ b/test/regress/regress1/aufbv/bug580.smt2 @@ -1,5 +1,5 @@ (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_AUFBV) diff --git a/test/regress/regress1/auflia/bug330.smt2 b/test/regress/regress1/auflia/bug330.smt2 index ce787e2e7..ada1fd8d5 100644 --- a/test/regress/regress1/auflia/bug330.smt2 +++ b/test/regress/regress1/auflia/bug330.smt2 @@ -6,7 +6,7 @@ Barrett at barrett@cs.stanford.edu for more information. This benchmark was automatically translated into SMT-LIB format from CVC format using CVC Lite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (set-info :difficulty | 0 |) diff --git a/test/regress/regress1/bug512.smt2 b/test/regress/regress1/bug512.smt2 index 1c8a0626a..6932e8d5d 100644 --- a/test/regress/regress1/bug512.smt2 +++ b/test/regress/regress1/bug512.smt2 @@ -3,7 +3,7 @@ ; EXPECT: (:reason-unknown incomplete) ; EXPECT: unsat (set-option :print-success false) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) ;(set-option :AUTO_CONFIG false) ;(set-option :MODEL_HIDE_UNUSED_PARTITIONS false) ;(set-option :MODEL_V2 true) diff --git a/test/regress/regress1/bug521.smt2 b/test/regress/regress1/bug521.smt2 index 8f840a1f6..73153e71b 100644 --- a/test/regress/regress1/bug521.smt2 +++ b/test/regress/regress1/bug521.smt2 @@ -1,7 +1,7 @@ ;(set-option :produce-unsat-cores true) (set-option :incremental true) (set-option :print-success false) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (set-option :produce-models true) (set-logic ALL_SUPPORTED) diff --git a/test/regress/regress1/bug590.smt2 b/test/regress/regress1/bug590.smt2 index d50024268..68a2fb9a3 100644 --- a/test/regress/regress1/bug590.smt2 +++ b/test/regress/regress1/bug590.smt2 @@ -4,7 +4,7 @@ (set-logic ALL) (set-option :strings-exp true) (set-option :produce-models true) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unknown) (declare-fun text () String) @@ -21,7 +21,7 @@ (assert (= html_escape_table (store (store (store (store (store ((as const (Array String String)) "A") "&" "&") - "\"" """) + "\\""" """) "'" "'") ">" ">") "<" "<"))) @@ -29,7 +29,7 @@ (assert (= html_escape_table_keys (store (store (store (store (store ((as const (Array Int String)) "B") 0 "&") - 1 "\"") + 1 "\\""") 2 "'") 3 ">") 4 "<"))) diff --git a/test/regress/regress1/bug800.smt2 b/test/regress/regress1/bug800.smt2 index d36f62b16..b62be95bd 100644 --- a/test/regress/regress1/bug800.smt2 +++ b/test/regress/regress1/bug800.smt2 @@ -3,7 +3,7 @@ ; EXPECT: sat (set-logic QF_UFLRA) (set-info :source |CPAchecker with bounded model checking on SV-COMP14 program using MathSAT5, submitted by Philipp Wendler, http://cpachecker.sosy-lab.org|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") diff --git a/test/regress/regress1/bv/decision-weight00.smt2 b/test/regress/regress1/bv/decision-weight00.smt2 index be52810e0..5d851f0d4 100644 --- a/test/regress/regress1/bv/decision-weight00.smt2 +++ b/test/regress/regress1/bv/decision-weight00.smt2 @@ -5,7 +5,7 @@ Patrice Godefroid, SAGE (systematic dynamic test generation) For more information: http://research.microsoft.com/en-us/um/people/pg/public_psfiles/ndss2008.pdf |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unknown) (declare-fun x () (_ BitVec 32)) diff --git a/test/regress/regress1/bvdiv2.smt2 b/test/regress/regress1/bvdiv2.smt2 index 7a8fc3753..67d583c76 100644 --- a/test/regress/regress1/bvdiv2.smt2 +++ b/test/regress/regress1/bvdiv2.smt2 @@ -1,5 +1,5 @@ (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun x0 () (_ BitVec 10)) diff --git a/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2 b/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2 index f2a5b81c8..f7c13722b 100644 --- a/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2 +++ b/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2 @@ -1,16 +1,9 @@ ; COMMAND-LINE: --fmf-fun-rlv --no-check-models ; EXPECT: sat -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic ALL) -(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String))) - (a1(c1$0)(c1$1)(c1$2)) - (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool))) - (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String))) - (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2)) - (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6)) - (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6)) - (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool))))) +(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool))))) (define-funs-rec ((f0((v0 a6))a4)) (c4$2)) (check-sat) diff --git a/test/regress/regress1/datatypes/issue3266-small.smt2 b/test/regress/regress1/datatypes/issue3266-small.smt2 index c57268cc9..d4b09e5ef 100644 --- a/test/regress/regress1/datatypes/issue3266-small.smt2 +++ b/test/regress/regress1/datatypes/issue3266-small.smt2 @@ -5,10 +5,10 @@ ; EXPECT: sat
; EXPECT: sat
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a8)(c0$3$1 Int))(c0$4(c0$4$0 a5)(c0$4$1 a6))(c0$5)(c0$6)(c0$7)(c0$8))(a1(c1$0)(c1$1(c1$1$0 a4)(c1$1$1 Bool)(c1$1$2 a6)(c1$1$3 a4)(c1$1$4 ab)(c1$1$5 Int)(c1$1$6 a0))(c1$2)(c1$3)(c1$4)(c1$5(c1$5$0 a7))(c1$6(c1$6$0 String)(c1$6$1 a4)(c1$6$2 a4)(c1$6$3 a0))(c1$7))(a2(c2$0)(c2$1(c2$1$0 aa)(c2$1$1 aa)(c2$1$2 a1)(c2$1$3 a0)(c2$1$4 a0)(c2$1$5 a0)(c2$1$6 a9))(c2$2(c2$2$0 a5)(c2$2$1 ab))(c2$3(c2$3$0 Bool)(c2$3$1 a7)(c2$3$2 a3)(c2$3$3 Bool)(c2$3$4 a0)(c2$3$5 String))(c2$4))(a3(c3$0(c3$0$0 a7))(c3$1)(c3$2)(c3$3)(c3$4)(c3$5)(c3$6)(c3$7)(c3$8)(c3$9)(c3$a)(c3$b)(c3$c))(a4(c4$0(c4$0$0 a2)(c4$0$1 a1)(c4$0$2 Bool)(c4$0$3 String)(c4$0$4 a3)(c4$0$5 Int)(c4$0$6 a2)))(a5(c5$0)(c5$1)(c5$2(c5$2$0 String))(c5$3)(c5$4)(c5$5)(c5$6(c5$6$0 a0)(c5$6$1 a6)(c5$6$2 a3)(c5$6$3 a3)(c5$6$4 a9))(c5$7))(a6(c6$0)(c6$1(c6$1$0 a7))(c6$2)(c6$3)(c6$4(c6$4$0 a7)(c6$4$1 a3)(c6$4$2 a4))(c6$5(c6$5$0 a9)(c6$5$1 a9)(c6$5$2 a7)(c6$5$3 a6)(c6$5$4 ab)(c6$5$5 a5)(c6$5$6 a3)(c6$5$7 aa))(c6$6)(c6$7)(c6$8)(c6$9)(c6$a)(c6$b)(c6$c))(a7(c7$0)(c7$1)(c7$2)(c7$3(c7$3$0 a8)(c7$3$1 Bool)(c7$3$2 Int)(c7$3$3 a5)(c7$3$4 a8))(c7$4)(c7$5)(c7$6)(c7$7)(c7$8(c7$8$0 a5)(c7$8$1 a1)))(a8(c8$0(c8$0$0 a6)(c8$0$1 ab)(c8$0$2 ab)(c8$0$3 a1)(c8$0$4 Bool))(c8$1(c8$1$0 a4)(c8$1$1 Bool)(c8$1$2 a2)(c8$1$3 String)(c8$1$4 Bool)))(a9(c9$0(c9$0$0 String))(c9$1(c9$1$0 String)(c9$1$1 ab))(c9$2(c9$2$0 a5)(c9$2$1 a9))(c9$3(c9$3$0 String)(c9$3$1 a8)(c9$3$2 a6))(c9$4)(c9$5))(aa(ca$0(ca$0$0 String)(ca$0$1 a3)(ca$0$2 a9)(ca$0$3 a3)(ca$0$4 Bool)(ca$0$5 a1)(ca$0$6 a1)(ca$0$7 a4))(ca$1)(ca$2(ca$2$0 a4)(ca$2$1 String)(ca$2$2 aa)(ca$2$3 ab)))(ab(cb$0(cb$0$0 a5)(cb$0$1 a2)(cb$0$2 a3)(cb$0$3 aa)(cb$0$4 Bool))(cb$1(cb$1$0 a0))(cb$2)(cb$3)(cb$4)(cb$5)(cb$6)(cb$7(cb$7$0 String)(cb$7$1 a0)(cb$7$2 a7)(cb$7$3 ab)(cb$7$4 aa)(cb$7$5 a8))(cb$8))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)(a8 0)(a9 0)(aa 0)(ab 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a8) (c0$3$1 Int)) (c0$4 (c0$4$0 a5) (c0$4$1 a6)) (c0$5) (c0$6) (c0$7) (c0$8))((c1$0) (c1$1 (c1$1$0 a4) (c1$1$1 Bool) (c1$1$2 a6) (c1$1$3 a4) (c1$1$4 ab) (c1$1$5 Int) (c1$1$6 a0)) (c1$2) (c1$3) (c1$4) (c1$5 (c1$5$0 a7)) (c1$6 (c1$6$0 String) (c1$6$1 a4) (c1$6$2 a4) (c1$6$3 a0)) (c1$7))((c2$0) (c2$1 (c2$1$0 aa) (c2$1$1 aa) (c2$1$2 a1) (c2$1$3 a0) (c2$1$4 a0) (c2$1$5 a0) (c2$1$6 a9)) (c2$2 (c2$2$0 a5) (c2$2$1 ab)) (c2$3 (c2$3$0 Bool) (c2$3$1 a7) (c2$3$2 a3) (c2$3$3 Bool) (c2$3$4 a0) (c2$3$5 String)) (c2$4))((c3$0 (c3$0$0 a7)) (c3$1) (c3$2) (c3$3) (c3$4) (c3$5) (c3$6) (c3$7) (c3$8) (c3$9) (c3$a) (c3$b) (c3$c))((c4$0 (c4$0$0 a2) (c4$0$1 a1) (c4$0$2 Bool) (c4$0$3 String) (c4$0$4 a3) (c4$0$5 Int) (c4$0$6 a2)))((c5$0) (c5$1) (c5$2 (c5$2$0 String)) (c5$3) (c5$4) (c5$5) (c5$6 (c5$6$0 a0) (c5$6$1 a6) (c5$6$2 a3) (c5$6$3 a3) (c5$6$4 a9)) (c5$7))((c6$0) (c6$1 (c6$1$0 a7)) (c6$2) (c6$3) (c6$4 (c6$4$0 a7) (c6$4$1 a3) (c6$4$2 a4)) (c6$5 (c6$5$0 a9) (c6$5$1 a9) (c6$5$2 a7) (c6$5$3 a6) (c6$5$4 ab) (c6$5$5 a5) (c6$5$6 a3) (c6$5$7 aa)) (c6$6) (c6$7) (c6$8) (c6$9) (c6$a) (c6$b) (c6$c))((c7$0) (c7$1) (c7$2) (c7$3 (c7$3$0 a8) (c7$3$1 Bool) (c7$3$2 Int) (c7$3$3 a5) (c7$3$4 a8)) (c7$4) (c7$5) (c7$6) (c7$7) (c7$8 (c7$8$0 a5) (c7$8$1 a1)))((c8$0 (c8$0$0 a6) (c8$0$1 ab) (c8$0$2 ab) (c8$0$3 a1) (c8$0$4 Bool)) (c8$1 (c8$1$0 a4) (c8$1$1 Bool) (c8$1$2 a2) (c8$1$3 String) (c8$1$4 Bool)))((c9$0 (c9$0$0 String)) (c9$1 (c9$1$0 String) (c9$1$1 ab)) (c9$2 (c9$2$0 a5) (c9$2$1 a9)) (c9$3 (c9$3$0 String) (c9$3$1 a8) (c9$3$2 a6)) (c9$4) (c9$5))((ca$0 (ca$0$0 String) (ca$0$1 a3) (ca$0$2 a9) (ca$0$3 a3) (ca$0$4 Bool) (ca$0$5 a1) (ca$0$6 a1) (ca$0$7 a4)) (ca$1) (ca$2 (ca$2$0 a4) (ca$2$1 String) (ca$2$2 aa) (ca$2$3 ab)))((cb$0 (cb$0$0 a5) (cb$0$1 a2) (cb$0$2 a3) (cb$0$3 aa) (cb$0$4 Bool)) (cb$1 (cb$1$0 a0)) (cb$2) (cb$3) (cb$4) (cb$5) (cb$6) (cb$7 (cb$7$0 String) (cb$7$1 a0) (cb$7$2 a7) (cb$7$3 ab) (cb$7$4 aa) (cb$7$5 a8)) (cb$8))))
(push 1)
(declare-fun v0() a0)
(push 1)
diff --git a/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2 b/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2 index cfb036f16..963e270a6 100644 --- a/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2 +++ b/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2 @@ -6,7 +6,7 @@ Boogie/Spec# benchmarks. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun InRange (Int Int) Bool) diff --git a/test/regress/regress1/fmf/issue916-fmf-or.smt2 b/test/regress/regress1/fmf/issue916-fmf-or.smt2 index 0c51e39af..479769188 100644 --- a/test/regress/regress1/fmf/issue916-fmf-or.smt2 +++ b/test/regress/regress1/fmf/issue916-fmf-or.smt2 @@ -2,7 +2,7 @@ ; EXPECT: sat (set-logic UFDTLIA) -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (define-funs-rec ( @@ -22,8 +22,8 @@ ) ) -(declare-datatypes (T) ( (List (Nil) (Cstr (head T) (tail List) ) ) ) ) -(declare-datatypes (T S) ( (Pair (Pair (first T) (second S)) ) ) ) +(declare-datatypes ((List 1)) ((par (T)((Nil) (Cstr (head T) (tail (List T))))))) +(declare-datatypes ((Pair 2)) ((par (T S)((Pair (first T) (second S)))))) (define-funs-rec ( diff --git a/test/regress/regress1/fmf/refcount24.cvc.smt2 b/test/regress/regress1/fmf/refcount24.cvc.smt2 index 2aaa28a3a..510e5c4db 100644 --- a/test/regress/regress1/fmf/refcount24.cvc.smt2 +++ b/test/regress/regress1/fmf/refcount24.cvc.smt2 @@ -1,15 +1,11 @@ ; COMMAND-LINE: --finite-model-find -q ; EXPECT: sat (set-logic ALL_SUPPORTED) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "unknown") (set-info :status sat) -(declare-datatypes () -((UNIT (Unit)) -)) -(declare-datatypes () -((BOOL (Truth) (Falsity)) -)) +(declare-datatype UNIT ((Unit))) +(declare-datatype BOOL ((Truth) (Falsity))) (declare-sort resource$type 0) (declare-sort process$type 0) (declare-fun null () resource$type) diff --git a/test/regress/regress1/fp/rti_3_5_bug_report.smt2 b/test/regress/regress1/fp/rti_3_5_bug_report.smt2 index 5a52ffcc9..3e94e6e05 100644 --- a/test/regress/regress1/fp/rti_3_5_bug_report.smt2 +++ b/test/regress/regress1/fp/rti_3_5_bug_report.smt2 @@ -1,20 +1,20 @@ -; REQUIRES: symfpu
-; COMMAND-LINE: --fp-exp
-; EXPECT: unsat
-
-(set-logic FP)
-(set-info :source |Written by Mathias Preiner for issue #2932|)
-(set-info :smt-lib-version 2.5)
-(set-info :category crafted)
-(set-info :status unsat)
-
-(define-sort FP () (_ FloatingPoint 3 5))
-(declare-const t FP)
-(assert
- (distinct
- (= t (fp.roundToIntegral RNA t))
- (exists ((x FP)) (= (fp.roundToIntegral RNA x) t))
- )
-)
-(check-sat)
-(exit)
+; REQUIRES: symfpu +; COMMAND-LINE: --fp-exp +; EXPECT: unsat + +(set-logic FP) +(set-info :source |Written by Mathias Preiner for issue #2932|) +(set-info :smt-lib-version 2.6) +(set-info :category crafted) +(set-info :status unsat) + +(define-sort FP () (_ FloatingPoint 3 5)) +(declare-const t FP) +(assert + (distinct + (= t (fp.roundToIntegral RNA t)) + (exists ((x FP)) (= (fp.roundToIntegral RNA x) t)) + ) +) +(check-sat) +(exit) diff --git a/test/regress/regress1/gensys_brn001.smt2 b/test/regress/regress1/gensys_brn001.smt2 index f3cc3c725..dab29c4b2 100644 --- a/test/regress/regress1/gensys_brn001.smt2 +++ b/test/regress/regress1/gensys_brn001.smt2 @@ -3,7 +3,7 @@ http://www.cs.bham.ac.uk/~vxs/quasigroups/benchmark/ |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-sort U 0) diff --git a/test/regress/regress1/nl/bug698.smt2 b/test/regress/regress1/nl/bug698.smt2 index ffb1eead2..f24d05372 100644 --- a/test/regress/regress1/nl/bug698.smt2 +++ b/test/regress/regress1/nl/bug698.smt2 @@ -1,6 +1,6 @@ ; COMMAND-LINE: --incremental --nl-ext --fmf-fun-rlv --no-check-models (set-logic UFNIA) -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) ; EXPECT: sat (declare-fun fixedAdd() Int) diff --git a/test/regress/regress1/nl/metitarski-1025.smt2 b/test/regress/regress1/nl/metitarski-1025.smt2 index 73a132350..3fbf9cb77 100644 --- a/test/regress/regress1/nl/metitarski-1025.smt2 +++ b/test/regress/regress1/nl/metitarski-1025.smt2 @@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun skoCOSS () Real) diff --git a/test/regress/regress1/nl/metitarski-3-4.smt2 b/test/regress/regress1/nl/metitarski-3-4.smt2 index 3a1e794cc..f26640f49 100644 --- a/test/regress/regress1/nl/metitarski-3-4.smt2 +++ b/test/regress/regress1/nl/metitarski-3-4.smt2 @@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun skoX () Real) diff --git a/test/regress/regress1/nl/metitarski_3_4_2e.smt2 b/test/regress/regress1/nl/metitarski_3_4_2e.smt2 index 3f12ec34b..07efc3d32 100644 --- a/test/regress/regress1/nl/metitarski_3_4_2e.smt2 +++ b/test/regress/regress1/nl/metitarski_3_4_2e.smt2 @@ -19,7 +19,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun skoX () Real) diff --git a/test/regress/regress1/nl/nl-help-unsat-quant.smt2 b/test/regress/regress1/nl/nl-help-unsat-quant.smt2 index f2f7667c8..d0acca99d 100644 --- a/test/regress/regress1/nl/nl-help-unsat-quant.smt2 +++ b/test/regress/regress1/nl/nl-help-unsat-quant.smt2 @@ -3,7 +3,7 @@ (set-logic UFNIA) (set-info :status unsat) (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (declare-sort S1 0) (declare-sort S2 0) diff --git a/test/regress/regress1/nl/nl-unk-quant.smt2 b/test/regress/regress1/nl/nl-unk-quant.smt2 index bb5cd43df..64cc419d7 100644 --- a/test/regress/regress1/nl/nl-unk-quant.smt2 +++ b/test/regress/regress1/nl/nl-unk-quant.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat (set-logic UFNIA) (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort S1 0) diff --git a/test/regress/regress1/nl/poly-1025.smt2 b/test/regress/regress1/nl/poly-1025.smt2 index 482696532..2fb918e3c 100644 --- a/test/regress/regress1/nl/poly-1025.smt2 +++ b/test/regress/regress1/nl/poly-1025.smt2 @@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun skoX () Real) diff --git a/test/regress/regress1/nl/quant-nl.smt2 b/test/regress/regress1/nl/quant-nl.smt2 index 7d251ab7d..f47023e99 100644 --- a/test/regress/regress1/nl/quant-nl.smt2 +++ b/test/regress/regress1/nl/quant-nl.smt2 @@ -3,7 +3,7 @@ (set-logic UFNIA) (set-info :status unsat) (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (declare-sort S1 0) (declare-sort S2 0) diff --git a/test/regress/regress1/proof00.smt2 b/test/regress/regress1/proof00.smt2 index 1b7e7b8dd..faae38923 100644 --- a/test/regress/regress1/proof00.smt2 +++ b/test/regress/regress1/proof00.smt2 @@ -7,7 +7,7 @@ CADE ATP System competition. See http://www.cs.miami.edu/~tptp/CASC This benchmark was obtained by trying to find a finite model of a first-order formula (Albert Oliveras). |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort U 0) diff --git a/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2 b/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2 index 670dcc006..ed5bf2a3d 100644 --- a/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2 +++ b/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2 @@ -3,7 +3,7 @@ Boogie/Spec# benchmarks. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun boolIff (Int Int) Int) diff --git a/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2 b/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2 index 3398f5f84..12a17cfe8 100644 --- a/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2 +++ b/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2 @@ -3,7 +3,7 @@ Boogie/Spec# benchmarks. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun InRange (Int Int) Bool) diff --git a/test/regress/regress1/quantifiers/array-unsat-simp3.smt2 b/test/regress/regress1/quantifiers/array-unsat-simp3.smt2 index 9dade2073..1666102e5 100644 --- a/test/regress/regress1/quantifiers/array-unsat-simp3.smt2 +++ b/test/regress/regress1/quantifiers/array-unsat-simp3.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --full-saturate-quant ; EXPECT: unsat (set-logic AUFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Index 0) diff --git a/test/regress/regress1/quantifiers/bignum_quant.smt2 b/test/regress/regress1/quantifiers/bignum_quant.smt2 index 74b08a2da..3e4cad64e 100644 --- a/test/regress/regress1/quantifiers/bignum_quant.smt2 +++ b/test/regress/regress1/quantifiers/bignum_quant.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | SMT-COMP'06 organizers |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "check") (set-info :status unsat) (set-info :notes |This benchmark is designed to check if the DP supports bignumbers.|) diff --git a/test/regress/regress1/quantifiers/bug802.smt2 b/test/regress/regress1/quantifiers/bug802.smt2 index 57da8510e..d5d0b0d7d 100644 --- a/test/regress/regress1/quantifiers/bug802.smt2 +++ b/test/regress/regress1/quantifiers/bug802.smt2 @@ -4,7 +4,7 @@ Hardware fixpoint check problems. These benchmarks stem from an evaluation described in Wintersteiger, Hamadi, de Moura: Efficiently solving quantified bit-vector formulas, FMSD 42(1), 2013. The hardware models that were used are from the VCEGAR benchmark suite (see www.cprover.org/hardware/). |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (assert (forall ((Verilog__main.reset_64_0 Bool)) (forall ((Verilog__main.rst_64_0 Bool)) (forall ((Verilog__main.usb_rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_0 Bool)) (forall ((Verilog__main.clk_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_0 Bool)) (forall ((Verilog__main.phy_tx_mode_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_0 Bool)) (forall ((Verilog__main.txdp_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_0 Bool)) (forall ((Verilog__main.txdn_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_0 Bool)) (forall ((Verilog__main.txoe_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_0 Bool)) (forall ((Verilog__main.TxValid_i_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_0 Bool)) (forall ((Verilog__main.TxReady_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_0 Bool)) (forall ((Verilog__main.rxd_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_0 Bool)) (forall ((Verilog__main.rxdp_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_0 Bool)) (forall ((Verilog__main.rxdn_64_0 Bool)) (forall ((Verilog__main.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_0 Bool)) (forall ((Verilog__main.RxActive_o_64_0 Bool)) (forall ((Verilog__main.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_0 Bool)) (forall ((Verilog__main.LineState_o_64_0 (_ BitVec 2))) (forall ((Verilog__main.reset_64_1 Bool)) (forall ((Verilog__main.rst_64_1 Bool)) (forall ((Verilog__main.usb_rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_1 Bool)) (forall ((Verilog__main.clk_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_1 Bool)) (forall ((Verilog__main.fs_ce_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_1 Bool)) (forall ((Verilog__main.phy_tx_mode_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_1 Bool)) (forall ((Verilog__main.txdp_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_1 Bool)) (forall ((Verilog__main.txdn_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_1 Bool)) (forall ((Verilog__main.txoe_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_1 Bool)) (forall ((Verilog__main.TxValid_i_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_1 Bool)) (forall ((Verilog__main.TxReady_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_1 Bool)) (forall ((Verilog__main.rxd_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_1 Bool)) (forall ((Verilog__main.rxdp_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_1 Bool)) (forall ((Verilog__main.rxdn_64_1 Bool)) (forall ((Verilog__main.DataIn_o_64_1 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_1 Bool)) (forall ((Verilog__main.RxActive_o_64_1 Bool)) (forall ((Verilog__main.RxError_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_1 Bool)) (forall ((Verilog__main.LineState_o_64_1 (_ BitVec 2))) (forall ((Verilog__main.reset_64_2 Bool)) (forall ((Verilog__main.rst_64_2 Bool)) (forall ((Verilog__main.usb_rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_2 Bool)) (forall ((Verilog__main.clk_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_2 Bool)) (forall ((Verilog__main.phy_tx_mode_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_2 Bool)) (forall ((Verilog__main.txdp_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_2 Bool)) (forall ((Verilog__main.txdn_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_2 Bool)) (forall ((Verilog__main.txoe_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_2 Bool)) (forall ((Verilog__main.TxValid_i_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_2 Bool)) (forall ((Verilog__main.TxReady_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_2 Bool)) (forall ((Verilog__main.rxd_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_2 Bool)) (forall ((Verilog__main.rxdp_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_2 Bool)) (forall ((Verilog__main.rxdn_64_2 Bool)) (forall ((Verilog__main.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_2 Bool)) (forall ((Verilog__main.RxActive_o_64_2 Bool)) (forall ((Verilog__main.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_2 Bool)) (forall ((Verilog__main.LineState_o_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_0 Bool)) (forall ((Verilog__main.rst_cnt_64_0 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_1 Bool)) (forall ((Verilog__main.rst_cnt_64_1 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_2 Bool)) (forall ((Verilog__main.rst_cnt_64_2 (_ BitVec 5))) (exists ((Verilog__main.reset_64_0_39_ Bool)) (exists ((Verilog__main.rst_64_0_39_ Bool)) (exists ((Verilog__main.usb_rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_0_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_0_39_ Bool)) (exists ((Verilog__main.txdp_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_0_39_ Bool)) (exists ((Verilog__main.txdn_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_0_39_ Bool)) (exists ((Verilog__main.txoe_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_0_39_ Bool)) (exists ((Verilog__main.rxd_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Bool)) (exists ((Verilog__main.LineState_o_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.reset_64_1_39_ Bool)) (exists ((Verilog__main.rst_64_1_39_ Bool)) (exists ((Verilog__main.usb_rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_1_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_1_39_ Bool)) (exists ((Verilog__main.txdp_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_1_39_ Bool)) (exists ((Verilog__main.txdn_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_1_39_ Bool)) (exists ((Verilog__main.txoe_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_1_39_ Bool)) (exists ((Verilog__main.rxd_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Bool)) (exists ((Verilog__main.LineState_o_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_0_39_ (_ BitVec 5))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_1_39_ (_ BitVec 5))) (=> (and (and (= Verilog__main.reset_64_0 (and Verilog__main.rst_64_0 (not Verilog__main.usb_rst_64_0))) (and (= Verilog__main.i_tx_phy.hold_64_0 Verilog__main.i_tx_phy.stuff_64_0) (= Verilog__main.i_tx_phy.sft_done_e_64_0 (and Verilog__main.i_tx_phy.sft_done_64_0 (not Verilog__main.i_tx_phy.sft_done_r_64_0))) (= Verilog__main.i_tx_phy.stuff_64_0 (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0)) (= Verilog__main.i_tx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_tx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_tx_phy.phy_mode_64_0 Verilog__main.phy_tx_mode_64_0) (= Verilog__main.i_tx_phy.txdp_64_0 Verilog__main.txdp_64_0) (= Verilog__main.i_tx_phy.txdn_64_0 Verilog__main.txdn_64_0) (= Verilog__main.i_tx_phy.txoe_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.DataOut_i_64_0) (= Verilog__main.i_tx_phy.TxValid_i_64_0 Verilog__main.TxValid_i_64_0) (= Verilog__main.i_tx_phy.TxReady_o_64_0 Verilog__main.TxReady_o_64_0) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.i_rx_phy.rx_active_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.i_rx_phy.rx_valid_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 false) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.i_rx_phy.hold_reg_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) Verilog__main.i_rx_phy.rxdn_s_64_0)) (= Verilog__main.i_rx_phy.j_64_0 (and Verilog__main.i_rx_phy.rxdp_s_64_0 (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.se0_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (= Verilog__main.i_rx_phy.change_64_0 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0 Verilog__main.i_rx_phy.rxdp_s1_64_0) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0 Verilog__main.i_rx_phy.rxdn_s1_64_0))) (= Verilog__main.i_rx_phy.drop_bit_64_0 (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_rx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_rx_phy.rxd_64_0 Verilog__main.rxd_64_0) (= Verilog__main.i_rx_phy.rxdp_64_0 Verilog__main.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdn_64_0 Verilog__main.rxdn_64_0) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.DataIn_o_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.RxValid_o_64_0) (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.RxActive_o_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 Verilog__main.RxError_o_64_0) (= Verilog__main.i_rx_phy.RxEn_i_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 Verilog__main.LineState_o_64_0)) (and (= Verilog__main.reset_64_1 (and Verilog__main.rst_64_1 (not Verilog__main.usb_rst_64_1))) (and (= Verilog__main.i_tx_phy.hold_64_1 Verilog__main.i_tx_phy.stuff_64_1) (= Verilog__main.i_tx_phy.sft_done_e_64_1 (and Verilog__main.i_tx_phy.sft_done_64_1 (not Verilog__main.i_tx_phy.sft_done_r_64_1))) (= Verilog__main.i_tx_phy.stuff_64_1 (= Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1)) (= Verilog__main.i_tx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_tx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_tx_phy.phy_mode_64_1 Verilog__main.phy_tx_mode_64_1) (= Verilog__main.i_tx_phy.txdp_64_1 Verilog__main.txdp_64_1) (= Verilog__main.i_tx_phy.txdn_64_1 Verilog__main.txdn_64_1) (= Verilog__main.i_tx_phy.txoe_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.DataOut_i_64_1) (= Verilog__main.i_tx_phy.TxValid_i_64_1 Verilog__main.TxValid_i_64_1) (= Verilog__main.i_tx_phy.TxReady_o_64_1 Verilog__main.TxReady_o_64_1) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.i_rx_phy.rx_active_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.i_rx_phy.rx_valid_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 false) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.i_rx_phy.hold_reg_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) Verilog__main.i_rx_phy.rxdn_s_64_1)) (= Verilog__main.i_rx_phy.j_64_1 (and Verilog__main.i_rx_phy.rxdp_s_64_1 (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.se0_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (= Verilog__main.i_rx_phy.change_64_1 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_1) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_1))) (= Verilog__main.i_rx_phy.drop_bit_64_1 (= Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_rx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_rx_phy.rxd_64_1 Verilog__main.rxd_64_1) (= Verilog__main.i_rx_phy.rxdp_64_1 Verilog__main.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdn_64_1 Verilog__main.rxdn_64_1) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.DataIn_o_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.RxValid_o_64_1) (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.RxActive_o_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 Verilog__main.RxError_o_64_1) (= Verilog__main.i_rx_phy.RxEn_i_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 Verilog__main.LineState_o_64_1)) (and (= Verilog__main.reset_64_2 (and Verilog__main.rst_64_2 (not Verilog__main.usb_rst_64_2))) (and (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.stuff_64_2) (= Verilog__main.i_tx_phy.sft_done_e_64_2 (and Verilog__main.i_tx_phy.sft_done_64_2 (not Verilog__main.i_tx_phy.sft_done_r_64_2))) (= Verilog__main.i_tx_phy.stuff_64_2 (= Verilog__main.i_tx_phy.one_cnt_64_2 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_2)) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.phy_tx_mode_64_2) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.txdp_64_2) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.txdn_64_2) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.DataOut_i_64_2) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.TxValid_i_64_2) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.TxReady_o_64_2) (and (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.rx_active_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.rx_valid_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 false) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.hold_reg_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_2 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_2 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) Verilog__main.i_rx_phy.rxdn_s_64_2)) (= Verilog__main.i_rx_phy.j_64_2 (and Verilog__main.i_rx_phy.rxdp_s_64_2 (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.se0_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.rx_en_64_2) (= Verilog__main.i_rx_phy.change_64_2 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_2) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_2))) (= Verilog__main.i_rx_phy.drop_bit_64_2 (= Verilog__main.i_rx_phy.one_cnt_64_2 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.rxd_64_2) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.rxdp_64_2) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.rxdn_64_2) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.DataIn_o_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.RxValid_o_64_2) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.RxActive_o_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.RxError_o_64_2) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.LineState_o_64_2)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0 false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0 true) (= Verilog__main.i_tx_phy.append_eop_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0 false) (= Verilog__main.i_tx_phy.txoe_r1_64_0 false) (= Verilog__main.i_tx_phy.txoe_r2_64_0 false) (= Verilog__main.i_tx_phy.txdp_64_0 true) (= Verilog__main.i_tx_phy.txdn_64_0 false) (= Verilog__main.i_tx_phy.txoe_64_0 true) (= Verilog__main.i_tx_phy.TxReady_o_64_0 false) (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0 false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0 false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0 false) (= Verilog__main.i_tx_phy.ld_data_d_64_0 false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0 false) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0 false) (= Verilog__main.i_tx_phy.data_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_r_64_0 false) (= Verilog__main.i_tx_phy.ld_data_64_0 false) (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0 false) (= Verilog__main.i_rx_phy.rxd_t1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s_64_0 false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s_64_0 false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s_64_0 false) (= Verilog__main.i_rx_phy.synced_d_64_0 false) (= Verilog__main.i_rx_phy.rx_en_64_0 false) (= Verilog__main.i_rx_phy.rx_active_64_0 false) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0 false) (= Verilog__main.i_rx_phy.rx_valid_64_0 false) (= Verilog__main.i_rx_phy.shift_en_64_0 false) (= Verilog__main.i_rx_phy.sd_r_64_0 false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0 false) (= Verilog__main.i_rx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0 false) (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0 false)) (= Verilog__main.usb_rst_64_0 false) (= Verilog__main.rst_cnt_64_0 (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite Verilog__main.i_tx_phy.stuff_64_0 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (not Verilog__main.i_tx_phy.txoe_r1_64_0)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.sd_bs_o_64_0 Verilog__main.i_tx_phy.sd_nrzi_o_64_0 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0)))) (= Verilog__main.i_tx_phy.append_eop_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0 false Verilog__main.i_tx_phy.append_eop_64_0)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0))) (= Verilog__main.i_tx_phy.txoe_r1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0))) (= Verilog__main.i_tx_phy.txoe_r2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0))) (= Verilog__main.i_tx_phy.txdp_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.txdp_64_0))) (= Verilog__main.i_tx_phy.txdn_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.txdn_64_0))) (= Verilog__main.i_tx_phy.txoe_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (not (or Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0)) Verilog__main.i_tx_phy.txoe_64_0))) (= Verilog__main.i_tx_phy.TxReady_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0 Verilog__main.i_tx_phy.TxValid_i_64_0))) (= Verilog__main.i_tx_phy.state_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 (_ bv1 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 (_ bv3 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0 (_ bv5 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0) Verilog__main.i_tx_phy.fs_ce_64_0) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (_ bv0 3) Verilog__main.i_tx_phy.state_64_0) Verilog__main.i_tx_phy.state_64_0)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1 Verilog__main.i_tx_phy.tx_ready_d_64_0) (= Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.tx_ready_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_sop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_data_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_eop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 true (ite Verilog__main.i_tx_phy.eop_done_64_0 false Verilog__main.i_tx_phy.tx_ip_64_0)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0))) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0 (not Verilog__main.i_tx_phy.hold_64_0)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0)))) (= Verilog__main.i_tx_phy.hold_reg_64_1 (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0 Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.i_tx_phy.hold_reg_64_0))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0 (not Verilog__main.i_tx_phy.tx_ip_64_0)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0) false Verilog__main.i_tx_phy.data_done_64_0)))) (= Verilog__main.i_tx_phy.sft_done_64_1 (and (not Verilog__main.i_tx_phy.hold_64_0) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1 Verilog__main.i_tx_phy.sft_done_64_0) (= Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.ld_data_d_64_0) (= Verilog__main.i_tx_phy.one_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0) Verilog__main.i_tx_phy.stuff_64_0) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.fs_ce_r3_64_0) (= Verilog__main.i_rx_phy.rxd_t1_64_1 Verilog__main.i_rx_phy.rxd_64_0) (= Verilog__main.i_rx_phy.rxd_s1_64_1 Verilog__main.i_rx_phy.rxd_t1_64_0) (= Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.rxd_s1_64_0) (= Verilog__main.i_rx_phy.rxdp_t1_64_1 Verilog__main.i_rx_phy.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdp_s1_64_1 Verilog__main.i_rx_phy.rxdp_t1_64_0) (= Verilog__main.i_rx_phy.rxdp_s_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_t1_64_1 Verilog__main.i_rx_phy.rxdn_64_0) (= Verilog__main.i_rx_phy.rxdn_s1_64_1 Verilog__main.i_rx_phy.rxdn_t1_64_0) (= Verilog__main.i_rx_phy.rxdn_s_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.synced_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.synced_d_64_0 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1 Verilog__main.i_rx_phy.RxEn_i_64_0) (= Verilog__main.i_rx_phy.rx_active_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_en_64_0) true (ite (and Verilog__main.i_rx_phy.se0_64_0 Verilog__main.i_rx_phy.rx_valid_r_64_0) false Verilog__main.i_rx_phy.rx_active_64_0)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) false Verilog__main.i_rx_phy.rx_valid1_64_0)))) (= Verilog__main.i_rx_phy.rx_valid_64_1 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0) Verilog__main.i_rx_phy.rx_valid1_64_0) Verilog__main.i_rx_phy.fs_ce_64_0)) (= Verilog__main.i_rx_phy.shift_en_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (or Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_active_64_0) Verilog__main.i_rx_phy.shift_en_64_0)) (= Verilog__main.i_rx_phy.sd_r_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) Verilog__main.i_rx_phy.sd_nrzi_64_0))) (= Verilog__main.i_rx_phy.hold_reg_64_1 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.shift_en_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0)) Verilog__main.i_rx_phy.hold_reg_64_0)) (= Verilog__main.i_rx_phy.one_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0) Verilog__main.i_rx_phy.drop_bit_64_0) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0)))) (= Verilog__main.i_rx_phy.dpll_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.fs_ce_d_64_0 (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1 Verilog__main.i_rx_phy.fs_ce_d_64_0) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1 Verilog__main.i_rx_phy.fs_ce_r1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1 Verilog__main.i_rx_phy.fs_ce_r2_64_0) (= Verilog__main.i_rx_phy.fs_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0)))))))) Verilog__main.i_rx_phy.fs_state_64_0))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1 (ite Verilog__main.i_rx_phy.rx_valid_64_0 true (ite Verilog__main.i_rx_phy.fs_ce_64_0 false Verilog__main.i_rx_phy.rx_valid_r_64_0)))) (= Verilog__main.usb_rst_64_1 (= Verilog__main.rst_cnt_64_0 (_ bv31 5))) (= Verilog__main.rst_cnt_64_1 (ite (not Verilog__main.rst_64_0) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0) Verilog__main.fs_ce_64_0) (bvadd Verilog__main.rst_cnt_64_0 (_ bv1 5)) Verilog__main.rst_cnt_64_0))))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite Verilog__main.i_tx_phy.stuff_64_1 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_1 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_1))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (not Verilog__main.i_tx_phy.txoe_r1_64_1)) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.sd_bs_o_64_1 Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.sd_nrzi_o_64_1)))) (= Verilog__main.i_tx_phy.append_eop_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_1 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_1 false Verilog__main.i_tx_phy.append_eop_64_1)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1))) (= Verilog__main.i_tx_phy.txoe_r1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1))) (= Verilog__main.i_tx_phy.txoe_r2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1))) (= Verilog__main.i_tx_phy.txdp_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.txdp_64_1))) (= Verilog__main.i_tx_phy.txdn_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.txdn_64_1))) (= Verilog__main.i_tx_phy.txoe_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (not (or Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1)) Verilog__main.i_tx_phy.txoe_64_1))) (= Verilog__main.i_tx_phy.TxReady_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (and Verilog__main.i_tx_phy.tx_ready_d_64_1 Verilog__main.i_tx_phy.TxValid_i_64_1))) (= Verilog__main.i_tx_phy.state_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 (_ bv1 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 (_ bv3 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) (_ bv4 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_1 (_ bv5 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_1) Verilog__main.i_tx_phy.fs_ce_64_1) (_ bv6 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (_ bv0 3) Verilog__main.i_tx_phy.state_64_1) Verilog__main.i_tx_phy.state_64_1)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 true (ite Verilog__main.i_tx_phy.eop_done_64_1 false Verilog__main.i_tx_phy.tx_ip_64_1)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1))) (= Verilog__main.i_tx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_1 (not Verilog__main.i_tx_phy.hold_64_1)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_1)))) (= Verilog__main.i_tx_phy.hold_reg_64_2 (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.i_tx_phy.hold_reg_64_1))) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_1)))))))))) (= Verilog__main.i_tx_phy.data_done_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_1 (not Verilog__main.i_tx_phy.tx_ip_64_1)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_1) false Verilog__main.i_tx_phy.data_done_64_1)))) (= Verilog__main.i_tx_phy.sft_done_64_2 (and (not Verilog__main.i_tx_phy.hold_64_1) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_64_1) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1) (= Verilog__main.i_tx_phy.one_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_1) Verilog__main.i_tx_phy.stuff_64_1) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_1))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_64_1) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_64_1) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.synced_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.synced_d_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_1 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1) (= Verilog__main.i_rx_phy.rx_active_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_en_64_1) true (ite (and Verilog__main.i_rx_phy.se0_64_1 Verilog__main.i_rx_phy.rx_valid_r_64_1) false Verilog__main.i_rx_phy.rx_active_64_1)))) (= Verilog__main.i_rx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_1)))) (= Verilog__main.i_rx_phy.rx_valid1_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) false Verilog__main.i_rx_phy.rx_valid1_64_1)))) (= Verilog__main.i_rx_phy.rx_valid_64_2 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_1) Verilog__main.i_rx_phy.rx_valid1_64_1) Verilog__main.i_rx_phy.fs_ce_64_1)) (= Verilog__main.i_rx_phy.shift_en_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (or Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_active_64_1) Verilog__main.i_rx_phy.shift_en_64_1)) (= Verilog__main.i_rx_phy.sd_r_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.rx_active_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not (xor Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) Verilog__main.i_rx_phy.sd_nrzi_64_1))) (= Verilog__main.i_rx_phy.hold_reg_64_2 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.shift_en_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_1 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_1)) Verilog__main.i_rx_phy.hold_reg_64_1)) (= Verilog__main.i_rx_phy.one_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_1) Verilog__main.i_rx_phy.drop_bit_64_1) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_1)))) (= Verilog__main.i_rx_phy.dpll_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_1)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1) (= Verilog__main.i_rx_phy.fs_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_1) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_1)))))))) Verilog__main.i_rx_phy.fs_state_64_1))) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 (ite Verilog__main.i_rx_phy.rx_valid_64_1 true (ite Verilog__main.i_rx_phy.fs_ce_64_1 false Verilog__main.i_rx_phy.rx_valid_r_64_1)))) (= Verilog__main.usb_rst_64_2 (= Verilog__main.rst_cnt_64_1 (_ bv31 5))) (= Verilog__main.rst_cnt_64_2 (ite (not Verilog__main.rst_64_1) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_1 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_1) Verilog__main.fs_ce_64_1) (bvadd Verilog__main.rst_cnt_64_1 (_ bv1 5)) Verilog__main.rst_cnt_64_1)))))) (and (and (and (= Verilog__main.reset_64_0_39_ (and Verilog__main.rst_64_0_39_ (not Verilog__main.usb_rst_64_0_39_))) (and (= Verilog__main.i_tx_phy.hold_64_0_39_ Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (and Verilog__main.i_tx_phy.sft_done_64_0_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_0_39_))) (= Verilog__main.i_tx_phy.stuff_64_0_39_ (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_)) (= Verilog__main.i_tx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_0_39_ Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_0_39_ Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_0_39_ Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Verilog__main.TxReady_o_64_0_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) Verilog__main.i_rx_phy.rxdn_s_64_0_39_)) (= Verilog__main.i_rx_phy.j_64_0_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_0_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.se0_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_0_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_0_39_ (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_0_39_ Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_0_39_ Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_0_39_ Verilog__main.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ Verilog__main.LineState_o_64_0_39_)) (and (= Verilog__main.reset_64_1_39_ (and Verilog__main.rst_64_1_39_ (not Verilog__main.usb_rst_64_1_39_))) (and (= Verilog__main.i_tx_phy.hold_64_1_39_ Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_1_39_ (and Verilog__main.i_tx_phy.sft_done_64_1_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_1_39_))) (= Verilog__main.i_tx_phy.stuff_64_1_39_ (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_)) (= Verilog__main.i_tx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_1_39_ Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_1_39_ Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_1_39_ Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_1_39_ Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Verilog__main.TxReady_o_64_1_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) Verilog__main.i_rx_phy.rxdn_s_64_1_39_)) (= Verilog__main.i_rx_phy.j_64_1_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_1_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.se0_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.lock_en_64_1_39_ Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_1_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_1_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_1_39_ (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_1_39_ Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_1_39_ Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_1_39_ Verilog__main.rxdn_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ Verilog__main.LineState_o_64_1_39_)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ true) (= Verilog__main.i_tx_phy.append_eop_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r1_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r2_64_0_39_ false) (= Verilog__main.i_tx_phy.txdp_64_0_39_ true) (= Verilog__main.i_tx_phy.txdn_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_64_0_39_ true) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ false) (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ false) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ false) (= Verilog__main.i_tx_phy.data_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_r_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_64_0_39_ false) (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s_64_0_39_ false) (= Verilog__main.i_rx_phy.synced_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_en_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_active_64_0_39_ false) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_valid_64_0_39_ false) (= Verilog__main.i_rx_phy.shift_en_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_r_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ false) (= Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ false)) (= Verilog__main.usb_rst_64_0_39_ false) (= Verilog__main.rst_cnt_64_0_39_ (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite Verilog__main.i_tx_phy.stuff_64_0_39_ false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0_39_))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (not Verilog__main.i_tx_phy.txoe_r1_64_0_39_)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false Verilog__main.i_tx_phy.append_eop_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_))) (= Verilog__main.i_tx_phy.txdp_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.txdp_64_0_39_))) (= Verilog__main.i_tx_phy.txdn_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.txdn_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not (or Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_)) Verilog__main.i_tx_phy.txoe_64_0_39_))) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Verilog__main.i_tx_phy.TxValid_i_64_0_39_))) (= Verilog__main.i_tx_phy.state_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (_ bv1 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (_ bv3 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ (_ bv5 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0_39_) Verilog__main.i_tx_phy.fs_ce_64_0_39_) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (_ bv0 3) Verilog__main.i_tx_phy.state_64_0_39_) Verilog__main.i_tx_phy.state_64_0_39_)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1_39_ Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_data_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ false Verilog__main.i_tx_phy.tx_ip_64_0_39_)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_))) (= Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not Verilog__main.i_tx_phy.hold_64_0_39_)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_tx_phy.hold_reg_64_1_39_ (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0_39_ Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.i_tx_phy.hold_reg_64_0_39_))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0_39_)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (not Verilog__main.i_tx_phy.tx_ip_64_0_39_)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0_39_) false Verilog__main.i_tx_phy.data_done_64_0_39_)))) (= Verilog__main.i_tx_phy.sft_done_64_1_39_ (and (not Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_1_39_ Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) Verilog__main.i_tx_phy.stuff_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0_39_))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_1_39_ Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.synced_d_64_0_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0_39_ true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1_39_ Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) true (ite (and Verilog__main.i_rx_phy.se0_64_0_39_ Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) false Verilog__main.i_rx_phy.rx_active_64_0_39_)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) false Verilog__main.i_rx_phy.rx_valid1_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid_64_1_39_ (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0_39_) Verilog__main.i_rx_phy.rx_valid1_64_0_39_) Verilog__main.i_rx_phy.fs_ce_64_0_39_)) (= Verilog__main.i_rx_phy.shift_en_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (or Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) Verilog__main.i_rx_phy.shift_en_64_0_39_)) (= Verilog__main.i_rx_phy.sd_r_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) Verilog__main.i_rx_phy.sd_nrzi_64_0_39_))) (= Verilog__main.i_rx_phy.hold_reg_64_1_39_ (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.shift_en_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) Verilog__main.i_rx_phy.drop_bit_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.dpll_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0_39_)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0_39_) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0_39_)))))))) Verilog__main.i_rx_phy.fs_state_64_0_39_))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ (ite Verilog__main.i_rx_phy.rx_valid_64_0_39_ true (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ false Verilog__main.i_rx_phy.rx_valid_r_64_0_39_)))) (= Verilog__main.usb_rst_64_1_39_ (= Verilog__main.rst_cnt_64_0_39_ (_ bv31 5))) (= Verilog__main.rst_cnt_64_1_39_ (ite (not Verilog__main.rst_64_0_39_) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0_39_ (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0_39_) Verilog__main.fs_ce_64_0_39_) (bvadd Verilog__main.rst_cnt_64_0_39_ (_ bv1 5)) Verilog__main.rst_cnt_64_0_39_)))))) (or (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_0_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_0_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_0_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_0_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_0_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_0_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_0_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_0_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_0_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_0_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_0_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_0_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_0_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_0_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_0_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_0_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_0_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_0_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_0_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_0_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_0_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_0_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_0_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_0_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_0_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_0_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_0_39_)) (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_1_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_1_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_1_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_1_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_1_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_1_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_1_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_1_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_1_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_1_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_1_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_1_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_1_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_1_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_1_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_1_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_1_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_1_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_1_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_1_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_1_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_1_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_1_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_1_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_1_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_1_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_1_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_1_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_1_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_1_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_1_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_1_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_1_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_1_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_1_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_1_39_))))) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )) diff --git a/test/regress/regress1/quantifiers/bug_743.smt2 b/test/regress/regress1/quantifiers/bug_743.smt2 index 1b6b16535..8b20cf5ca 100644 --- a/test/regress/regress1/quantifiers/bug_743.smt2 +++ b/test/regress/regress1/quantifiers/bug_743.smt2 @@ -4,7 +4,7 @@ ;; produced by cvc4_14.drv ;; (set-logic AUFBVDTNIRA) (set-info :source |VC generated by SPARK 2014|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category industrial) (set-info :status unsat) ;;; generated by SMT-LIB2 driver diff --git a/test/regress/regress1/quantifiers/burns13.smt2 b/test/regress/regress1/quantifiers/burns13.smt2 index 3424c161e..592187f9d 100644 --- a/test/regress/regress1/quantifiers/burns13.smt2 +++ b/test/regress/regress1/quantifiers/burns13.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat (set-logic AUFLIA) (set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun s_0 (Int) Bool) diff --git a/test/regress/regress1/quantifiers/burns4.smt2 b/test/regress/regress1/quantifiers/burns4.smt2 index 72023fd4f..1601b101e 100644 --- a/test/regress/regress1/quantifiers/burns4.smt2 +++ b/test/regress/regress1/quantifiers/burns4.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat (set-logic AUFLIA) (set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun s_0 (Int) Bool) diff --git a/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2 b/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2 index e9f0490a6..f9386005d 100644 --- a/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2 +++ b/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2 @@ -5,7 +5,7 @@ Aerospace Software", IJCAR 2004. Translated from TPTP format by Yeting Ge and Clark Barrett |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun def () Real) diff --git a/test/regress/regress1/quantifiers/issue3316.smt2 b/test/regress/regress1/quantifiers/issue3316.smt2 index 320a57790..0e69410f7 100644 --- a/test/regress/regress1/quantifiers/issue3316.smt2 +++ b/test/regress/regress1/quantifiers/issue3316.smt2 @@ -1,16 +1,9 @@ ; COMMAND-LINE: --fmf-fun-rlv --no-check-models ; EXPECT: sat -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic ALL) -(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String))) - (a1(c1$0)(c1$1)(c1$2)) - (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool))) - (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String))) - (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2)) - (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6)) - (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6)) - (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool))))) +(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool))))) (define-funs-rec ((f3((v4 Bool))a7) (f2()a6) (f1((v1 a3)(v2 a1)(v3 Bool))String) diff --git a/test/regress/regress1/quantifiers/issue3317.smt2 b/test/regress/regress1/quantifiers/issue3317.smt2 index 57b353e28..758878af2 100644 --- a/test/regress/regress1/quantifiers/issue3317.smt2 +++ b/test/regress/regress1/quantifiers/issue3317.smt2 @@ -1,9 +1,9 @@ ; COMMAND-LINE: --fmf-fun-rlv --no-check-models ; EXPECT: sat -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic ALL) -(declare-datatypes () ((a0(c0$0(c0$0$0 a4)(c0$0$1 Bool)(c0$0$2 a4)(c0$0$3 Int)(c0$0$4 a5)(c0$0$5 a7)(c0$0$6 a7)))(a1(c1$0(c1$0$0 Bool)(c1$0$1 Bool)(c1$0$2 Int))(c1$1)(c1$2(c1$2$0 a3)(c1$2$1 a5)(c1$2$2 a1)(c1$2$3 a7))(c1$3)(c1$4)(c1$5)(c1$6)(c1$7)(c1$8)(c1$9(c1$9$0 a4))(c1$a))(a2(c2$0(c2$0$0 String)(c2$0$1 a4)(c2$0$2 a0)(c2$0$3 Bool)(c2$0$4 a5)(c2$0$5 a4))(c2$1)(c2$2)(c2$3)(c2$4)(c2$5))(a3(c3$0)(c3$1)(c3$2)(c3$3)(c3$4(c3$4$0 a6))(c3$5)(c3$6)(c3$7))(a4(c4$0)(c4$1(c4$1$0 a3))(c4$2(c4$2$0 a5))(c4$3)(c4$4)(c4$5(c4$5$0 String)(c4$5$1 a4))(c4$6)(c4$7)(c4$8)(c4$9(c4$9$0 String))(c4$a)(c4$b))(a5(c5$0)(c5$1(c5$1$0 a7)(c5$1$1 a0)(c5$1$2 Bool)(c5$1$3 a1)(c5$1$4 a3)(c5$1$5 a7)(c5$1$6 Int)(c5$1$7 Bool))(c5$2)(c5$3)(c5$4)(c5$5)(c5$6)(c5$7))(a6(c6$0(c6$0$0 Bool))(c6$1)(c6$2(c6$2$0 Bool)(c6$2$1 a3)(c6$2$2 Int)(c6$2$3 a3)(c6$2$4 a6)(c6$2$5 a7)(c6$2$6 a0)(c6$2$7 a6)))(a7(c7$0)(c7$1)(c7$2(c7$2$0 a6))(c7$3)(c7$4)(c7$5(c7$5$0 a2)(c7$5$1 a2)(c7$5$2 Int)(c7$5$3 a6))(c7$6)(c7$7)))) +(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0 (c0$0$0 a4) (c0$0$1 Bool) (c0$0$2 a4) (c0$0$3 Int) (c0$0$4 a5) (c0$0$5 a7) (c0$0$6 a7)))((c1$0 (c1$0$0 Bool) (c1$0$1 Bool) (c1$0$2 Int)) (c1$1) (c1$2 (c1$2$0 a3) (c1$2$1 a5) (c1$2$2 a1) (c1$2$3 a7)) (c1$3) (c1$4) (c1$5) (c1$6) (c1$7) (c1$8) (c1$9 (c1$9$0 a4)) (c1$a))((c2$0 (c2$0$0 String) (c2$0$1 a4) (c2$0$2 a0) (c2$0$3 Bool) (c2$0$4 a5) (c2$0$5 a4)) (c2$1) (c2$2) (c2$3) (c2$4) (c2$5))((c3$0) (c3$1) (c3$2) (c3$3) (c3$4 (c3$4$0 a6)) (c3$5) (c3$6) (c3$7))((c4$0) (c4$1 (c4$1$0 a3)) (c4$2 (c4$2$0 a5)) (c4$3) (c4$4) (c4$5 (c4$5$0 String) (c4$5$1 a4)) (c4$6) (c4$7) (c4$8) (c4$9 (c4$9$0 String)) (c4$a) (c4$b))((c5$0) (c5$1 (c5$1$0 a7) (c5$1$1 a0) (c5$1$2 Bool) (c5$1$3 a1) (c5$1$4 a3) (c5$1$5 a7) (c5$1$6 Int) (c5$1$7 Bool)) (c5$2) (c5$3) (c5$4) (c5$5) (c5$6) (c5$7))((c6$0 (c6$0$0 Bool)) (c6$1) (c6$2 (c6$2$0 Bool) (c6$2$1 a3) (c6$2$2 Int) (c6$2$3 a3) (c6$2$4 a6) (c6$2$5 a7) (c6$2$6 a0) (c6$2$7 a6)))((c7$0) (c7$1) (c7$2 (c7$2$0 a6)) (c7$3) (c7$4) (c7$5 (c7$5$0 a2) (c7$5$1 a2) (c7$5$2 Int) (c7$5$3 a6)) (c7$6) (c7$7)))) (define-funs-rec ( (f9((v38 Int)(v39 a2)(v3a a5)(v3b a0)(v3c a7)(v3d a3))Bool) (f8((v33 String)(v34 Int)(v35 a1)(v36 a7)(v37 a4))a6) (f7((v29 a1)(v2a Bool)(v2b a3)(v2c String)(v2d Bool)(v2e String)(v2f a7)(v30 a5)(v31 a2)(v32 a2))Int) diff --git a/test/regress/regress1/quantifiers/issue3765.smt2 b/test/regress/regress1/quantifiers/issue3765.smt2 index 97e106365..4947586f2 100644 --- a/test/regress/regress1/quantifiers/issue3765.smt2 +++ b/test/regress/regress1/quantifiers/issue3765.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --fmf-fun --no-check-models
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
(define-funs-rec (
diff --git a/test/regress/regress1/quantifiers/issue993.smt2 b/test/regress/regress1/quantifiers/issue993.smt2 index 40c5538de..aa0c29f5e 100644 --- a/test/regress/regress1/quantifiers/issue993.smt2 +++ b/test/regress/regress1/quantifiers/issue993.smt2 @@ -1,5 +1,5 @@ (set-logic AUFBVDTNIRA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status unsat) (declare-sort us_private 0) @@ -7,18 +7,13 @@ (declare-fun to_rep1 (integer) Int) -(declare-datatypes () -((us_split_fields - (mk___split_fields (rec__unit1__t1__c1 integer)(rec__ext__ us_private))))) +(declare-datatypes ((us_split_fields 0)) (((mk___split_fields (rec__unit1__t1__c1 integer) (rec__ext__ us_private))))) +(declare-datatypes ((us_split_fields__ref 0)) (((mk___split_fields__ref (us_split_fields__content us_split_fields))))) -(declare-datatypes () -((us_split_fields__ref - (mk___split_fields__ref (us_split_fields__content us_split_fields))))) (define-fun us_split_fields__ref___projection ((a us_split_fields__ref)) us_split_fields (us_split_fields__content a)) -(declare-datatypes () -((us_rep (mk___rep (us_split_fields1 us_split_fields)(attr__tag Int))))) +(declare-datatypes ((us_rep 0)) (((mk___rep (us_split_fields1 us_split_fields) (attr__tag Int))))) (define-fun us_rep___projection ((a us_rep)) us_split_fields (us_split_fields1 a)) @@ -34,19 +29,13 @@ (= (to_rep1 (rec__unit1__t1__c1 (us_split_fields1 x))) 0))) :pattern ( (is_zero x)) ))) -(declare-datatypes () -((us_split_fields2 - (mk___split_fields1 - (rec__unit2__t2__c2 integer)(rec__unit1__t1__c11 integer)(rec__ext__1 us_private))))) +(declare-datatypes ((us_split_fields2 0)) (((mk___split_fields1 (rec__unit2__t2__c2 integer) (rec__unit1__t1__c11 integer) (rec__ext__1 us_private))))) +(declare-datatypes ((us_split_fields__ref1 0)) (((mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2))))) -(declare-datatypes () -((us_split_fields__ref1 - (mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2))))) (define-fun us_split_fields__ref_2__projection ((a us_split_fields__ref1)) us_split_fields2 (us_split_fields__content1 a)) -(declare-datatypes () -((us_rep1 (mk___rep1 (us_split_fields3 us_split_fields2)(attr__tag1 Int))))) +(declare-datatypes ((us_rep1 0)) (((mk___rep1 (us_split_fields3 us_split_fields2) (attr__tag1 Int))))) (define-fun us_rep_3__projection ((a us_rep1)) us_split_fields2 (us_split_fields3 a)) diff --git a/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2 b/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2 index 1c3aa1d8b..03ae9fb62 100644 --- a/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2 +++ b/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2 @@ -3,7 +3,7 @@ Simplify front end test suite. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun after_133.8_133.8 () Int) diff --git a/test/regress/regress1/quantifiers/opisavailable-12.smt2 b/test/regress/regress1/quantifiers/opisavailable-12.smt2 index c529b409f..879fbf4e4 100644 --- a/test/regress/regress1/quantifiers/opisavailable-12.smt2 +++ b/test/regress/regress1/quantifiers/opisavailable-12.smt2 @@ -2,7 +2,7 @@ (set-info :source | Tokeneer case study <http://www.adacore.com/home/products/gnatpro/tokeneer/> |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun field.datat.length () Int) diff --git a/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2 b/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2 index 2a5eb34a7..20ab505d4 100644 --- a/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2 +++ b/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2 @@ -5,7 +5,7 @@ Simplify front end test suite. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun EC_134.22_134.22 () Int) diff --git a/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2 b/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2 index 6874c522e..a5e893d9b 100644 --- a/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2 +++ b/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat (set-logic AUFLIRA) (set-info :source |http://proval.lri.fr/why-benchmarks |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort Unit 0) diff --git a/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2 b/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2 index ec49231e3..3ce3b8406 100644 --- a/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2 +++ b/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2 @@ -1,5 +1,5 @@ (set-logic UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun boolIff (Int Int) Int) diff --git a/test/regress/regress1/quantifiers/ricart-agrawala6.smt2 b/test/regress/regress1/quantifiers/ricart-agrawala6.smt2 index 5f849de15..b6ba41b0e 100644 --- a/test/regress/regress1/quantifiers/ricart-agrawala6.smt2 +++ b/test/regress/regress1/quantifiers/ricart-agrawala6.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | An Optimal Algorithm for Mutual Exclusion in Computer Networks. Glenn Ricart and Ashok K. Agrawala. Communications of the ACM Vol.: 24 Number: 1. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun p () Int) diff --git a/test/regress/regress1/quantifiers/set3.smt2 b/test/regress/regress1/quantifiers/set3.smt2 index bd208c6d3..ce5665f86 100644 --- a/test/regress/regress1/quantifiers/set3.smt2 +++ b/test/regress/regress1/quantifiers/set3.smt2 @@ -1,7 +1,7 @@ ; COMMAND-LINE: --full-saturate-quant (set-logic AUFLIA) (set-info :source | Assertion verification of simple set manipulation programs. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Set 0) diff --git a/test/regress/regress1/quantifiers/set8.smt2 b/test/regress/regress1/quantifiers/set8.smt2 index 684d94b7a..bf0bb7130 100644 --- a/test/regress/regress1/quantifiers/set8.smt2 +++ b/test/regress/regress1/quantifiers/set8.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Set theory. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-sort Set 0) diff --git a/test/regress/regress1/quantifiers/smtlib384a03.smt2 b/test/regress/regress1/quantifiers/smtlib384a03.smt2 index 9e2273cff..af68776b2 100644 --- a/test/regress/regress1/quantifiers/smtlib384a03.smt2 +++ b/test/regress/regress1/quantifiers/smtlib384a03.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIRA) (set-info :source |http://proval.lri.fr/why-benchmarks |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort Unit 0) diff --git a/test/regress/regress1/quantifiers/smtlib46f14a.smt2 b/test/regress/regress1/quantifiers/smtlib46f14a.smt2 index fa0c85470..c550b308e 100644 --- a/test/regress/regress1/quantifiers/smtlib46f14a.smt2 +++ b/test/regress/regress1/quantifiers/smtlib46f14a.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIRA) (set-info :source |http://proval.lri.fr/why-benchmarks |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort Unit 0) diff --git a/test/regress/regress1/quantifiers/smtlibf957ea.smt2 b/test/regress/regress1/quantifiers/smtlibf957ea.smt2 index aa82255ef..1d6a7f577 100644 --- a/test/regress/regress1/quantifiers/smtlibf957ea.smt2 +++ b/test/regress/regress1/quantifiers/smtlibf957ea.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIRA) (set-info :source |http://proval.lri.fr/why-benchmarks |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort Unit 0) diff --git a/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2 b/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2 index ebf1f080e..ba5d012a0 100644 --- a/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2 +++ b/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2 @@ -3,7 +3,7 @@ (set-info :source | Example extracted from Peter Baumgartner's talk at CADE-21: Logical Engineering with Instance-Based Methods. It was translated to SMT-LIB by Leonardo de Moura |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun symmetric ((Array Int (Array Int Real)) Int) Bool) diff --git a/test/regress/regress1/quantifiers/var-eq-trigger.smt2 b/test/regress/regress1/quantifiers/var-eq-trigger.smt2 index bccc86e6f..970fea047 100644 --- a/test/regress/regress1/quantifiers/var-eq-trigger.smt2 +++ b/test/regress/regress1/quantifiers/var-eq-trigger.smt2 @@ -2,7 +2,7 @@ ; EXPECT: unsat (set-logic UFNIA) (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-sort S1 0) diff --git a/test/regress/regress1/sets/fuzz14418.smt2 b/test/regress/regress1/sets/fuzz14418.smt2 index 24679749c..9b65102a6 100644 --- a/test/regress/regress1/sets/fuzz14418.smt2 +++ b/test/regress/regress1/sets/fuzz14418.smt2 @@ -8,7 +8,7 @@ ; ; sat (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_UFLIAFS) diff --git a/test/regress/regress1/sets/fuzz15201.smt2 b/test/regress/regress1/sets/fuzz15201.smt2 index e12b74d18..f9dbaeb75 100644 --- a/test/regress/regress1/sets/fuzz15201.smt2 +++ b/test/regress/regress1/sets/fuzz15201.smt2 @@ -1,7 +1,7 @@ ; symptom: unsat instead of sat ; issue/fix: buggy rewriter for setminus (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_UFLIAFS) diff --git a/test/regress/regress1/sets/fuzz31811.smt2 b/test/regress/regress1/sets/fuzz31811.smt2 index 5e7c032ea..9a7a7510a 100644 --- a/test/regress/regress1/sets/fuzz31811.smt2 +++ b/test/regress/regress1/sets/fuzz31811.smt2 @@ -6,7 +6,7 @@ ; stop. ; (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_UFLIAFS) diff --git a/test/regress/regress1/sets/sharingbug.smt2 b/test/regress/regress1/sets/sharingbug.smt2 index b87579816..82c6eb8f0 100644 --- a/test/regress/regress1/sets/sharingbug.smt2 +++ b/test/regress/regress1/sets/sharingbug.smt2 @@ -1,5 +1,5 @@ (set-info :source |fuzzsmt|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (set-logic QF_UFLIAFS) diff --git a/test/regress/regress1/strings/bug686dd.smt2 b/test/regress/regress1/strings/bug686dd.smt2 index b5c9457ff..1449a09be 100644 --- a/test/regress/regress1/strings/bug686dd.smt2 +++ b/test/regress/regress1/strings/bug686dd.smt2 @@ -1,14 +1,13 @@ -(set-info :smt-lib-version 2.5) (set-logic UFDTSLIA) (set-info :status sat) -(declare-datatypes () ((T (TC (TCb String))))) +(declare-datatype T ((TC (TCb String)))) (declare-fun root5 () String) (declare-fun root6 () T) (assert (and -(str.in.re root5 ((_ re.loop 4 4) (re.range "0" "9")) ) -(str.in.re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) ) +(str.in_re root5 ((_ re.loop 4 4) (re.range "0" "9")) ) +(str.in_re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) ) ) ) (check-sat) diff --git a/test/regress/regress1/strings/issue1105.smt2 b/test/regress/regress1/strings/issue1105.smt2 index bf5cb7669..59f618403 100644 --- a/test/regress/regress1/strings/issue1105.smt2 +++ b/test/regress/regress1/strings/issue1105.smt2 @@ -1,11 +1,10 @@ -(set-info :smt-lib-version 2.5) (set-logic ALL) (set-option :strings-exp true) (set-info :status sat) -(declare-datatypes () ((Val - (Str (str String)) - (Num (num Int))))) +(declare-datatype Val + ((Str (str String)) + (Num (num Int)))) (declare-const var0 Val) -(assert (=> (is-Str var0) (distinct (str.to.int (str var0)) (- 1)))) +(assert (=> (is-Str var0) (distinct (str.to_int (str var0)) (- 1)))) (check-sat) diff --git a/test/regress/regress1/strings/issue1684-regex.smt2 b/test/regress/regress1/strings/issue1684-regex.smt2 index de0739bd8..41fa27120 100644 --- a/test/regress/regress1/strings/issue1684-regex.smt2 +++ b/test/regress/regress1/strings/issue1684-regex.smt2 @@ -1,8 +1,8 @@ -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-logic QF_S) (set-info :status sat) (set-option :strings-exp true) (declare-const s String) -(assert (str.in.re s (re.* (re.range "\x00" "\xFF")))) -(assert (str.in.re s (re.range "\x00" "\xFF"))) +(assert (str.in_re s (re.* (re.range "\u{0}" "\u{ff}")))) +(assert (str.in_re s (re.range "\u{0}" "\u{ff}"))) (check-sat) diff --git a/test/regress/regress1/strings/issue3272.smt2 b/test/regress/regress1/strings/issue3272.smt2 index cf33afb92..622e294d8 100644 --- a/test/regress/regress1/strings/issue3272.smt2 +++ b/test/regress/regress1/strings/issue3272.smt2 @@ -1,4 +1,4 @@ -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-logic ALL_SUPPORTED) (set-option :strings-exp true) (set-info :status sat) @@ -9,13 +9,13 @@ (and (and (and - (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\t") 1 0) 0)) + (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\u{9}") 1 0) 0)) (= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) "B") 1 0) 0) ) (= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len c) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) " ") 1 0) 0) - (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\v") 1 0) 0)) + (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\u{b}") 1 0) 0)) ) (= (ite (= (str.at (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0) " ") 1 0) 0) ) diff --git a/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2 b/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2 index b2bb29577..4879cb3fb 100644 --- a/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2 +++ b/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2 @@ -10,10 +10,10 @@ ; EXPECT: sat
; EXPECT: sat
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a1)(c0$3$1 Int)(c0$3$2 String)(c0$3$3 Int))(c0$4(c0$4$0 Int))(c0$5))(a1(c1$0(c1$0$0 a0)(c1$0$1 a0)(c1$0$2 String)(c1$0$3 Int))(c1$1(c1$1$0 Int))(c1$2)(c1$3(c1$3$0 Int))(c1$4)(c1$5))(a2(c2$0(c2$0$0 Int)(c2$0$1 a0))(c2$1(c2$1$0 String)(c2$1$1 a0)(c2$1$2 a1)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a1) (c0$3$1 Int) (c0$3$2 String) (c0$3$3 Int)) (c0$4 (c0$4$0 Int)) (c0$5))((c1$0 (c1$0$0 a0) (c1$0$1 a0) (c1$0$2 String) (c1$0$3 Int)) (c1$1 (c1$1$0 Int)) (c1$2) (c1$3 (c1$3$0 Int)) (c1$4) (c1$5))((c2$0 (c2$0$0 Int) (c2$0$1 a0)) (c2$1 (c2$1$0 String) (c2$1$1 a0) (c2$1$2 a1)))))
(push 1)
(pop 1)
(push 1)
diff --git a/test/regress/regress1/strings/pierre150331.smt2 b/test/regress/regress1/strings/pierre150331.smt2 index ae4277874..562904366 100644 --- a/test/regress/regress1/strings/pierre150331.smt2 +++ b/test/regress/regress1/strings/pierre150331.smt2 @@ -1,13 +1,13 @@ -(set-info :smt-lib-version 2.5)
-(set-logic SLIA)
-(set-info :status sat)
-(set-option :strings-exp true)
-(define-fun stringEval ((?s String)) Bool (str.in.re ?s
-(re.union
-(str.to.re "H")
-(re.++ ((_ re.loop 2 2) (str.to.re "{") ) ((_ re.loop 2 4) (re.union re.nostr (re.range " " "]") (re.range "" "^") ) ) ) ) ) )
-(declare-fun s0() String)
-(declare-fun s1() String)
-(declare-fun s2() String)
-(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) )
-(check-sat)
+(set-info :smt-lib-version 2.6) +(set-logic SLIA) +(set-info :status sat) +(set-option :strings-exp true) +(define-fun stringEval ((?s String)) Bool (str.in_re ?s +(re.union +(str.to_re "H") +(re.++ ((_ re.loop 2 2) (str.to_re "{") ) ((_ re.loop 2 4) (re.union re.none (re.range "\u{1d}" "]") (re.range "\u{e}" "^") ) ) ) ) ) ) +(declare-fun s0() String) +(declare-fun s1() String) +(declare-fun s2() String) +(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) ) +(check-sat) diff --git a/test/regress/regress1/uf2.smt2 b/test/regress/regress1/uf2.smt2 index 0aa1617eb..1dc17b045 100644 --- a/test/regress/regress1/uf2.smt2 +++ b/test/regress/regress1/uf2.smt2 @@ -1,5 +1,5 @@ (set-logic QF_AUFBVLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status unsat) (declare-fun v1 () (_ BitVec 1)) diff --git a/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2 b/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2 index 84ed4b199..c18486fce 100644 --- a/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2 +++ b/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2 @@ -2,7 +2,7 @@ ; EXPECT: sat (set-logic QF_UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (declare-fun _base () Int) (declare-fun _n () Int) (declare-fun ___z3z___ (Int) Bool) diff --git a/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2 b/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2 index 248a056d3..f7e670a2c 100644 --- a/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2 +++ b/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2 @@ -1,5 +1,5 @@ (set-logic QF_UFLIA) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :status sat) (declare-fun _base () Int) (declare-fun _n () Int) diff --git a/test/regress/regress1/uflia/simple_cyclic2.smt2 b/test/regress/regress1/uflia/simple_cyclic2.smt2 index 7a0b39999..57fd60b89 100644 --- a/test/regress/regress1/uflia/simple_cyclic2.smt2 +++ b/test/regress/regress1/uflia/simple_cyclic2.smt2 @@ -5,7 +5,7 @@ Benchmark generated from the verification of programs manipulating linked lists This benchmark was automatically translated into SMT-LIB format by Albert Oliveras. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun t.l () Int) diff --git a/test/regress/regress2/DTP_k2_n35_c175_s15.smt2 b/test/regress/regress2/DTP_k2_n35_c175_s15.smt2 index 20f4bf5a9..9a20c82ac 100644 --- a/test/regress/regress2/DTP_k2_n35_c175_s15.smt2 +++ b/test/regress/regress2/DTP_k2_n35_c175_s15.smt2 @@ -5,7 +5,7 @@ http://www.ai.dist.unige.it/Tsat for more information. Translated into SMT-LIB format by Albert Oliveras. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "random") (set-info :status sat) (declare-fun x10 () Int) diff --git a/test/regress/regress2/arith/miplib-opt1217--27.smt2 b/test/regress/regress2/arith/miplib-opt1217--27.smt2 index 2adcdd3a9..802839bb8 100644 --- a/test/regress/regress2/arith/miplib-opt1217--27.smt2 +++ b/test/regress/regress2/arith/miplib-opt1217--27.smt2 @@ -6,7 +6,7 @@ Relaxation of the Mixed-Integer Programming optimization problem opt1217 from the MIPLIB (http://miplib.zib.de/) by Enric Rodriguez-Carbonell (erodri@lsi.upc.edu) |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun tmp766 () Real) diff --git a/test/regress/regress2/bug394.smt2 b/test/regress/regress2/bug394.smt2 index 99e19e7fb..79fbf2e44 100644 --- a/test/regress/regress2/bug394.smt2 +++ b/test/regress/regress2/bug394.smt2 @@ -13,7 +13,7 @@ ; EXPECT: sat ;(set-option :produce-unsat-cores true) (set-option :print-success false) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) ;(set-option :produce-models true) (set-logic ALL_SUPPORTED) ; done setting options diff --git a/test/regress/regress2/bug812.smt2 b/test/regress/regress2/bug812.smt2 index 8bc87fa52..79eb1c72c 100644 --- a/test/regress/regress2/bug812.smt2 +++ b/test/regress/regress2/bug812.smt2 @@ -3,7 +3,7 @@ VCC and HAVOC benchmarks. Contributed by Nikolaj Bjorner, Leonardo de Moura,
Michal Moskal, and Shaz Qadeer.
|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun x (Int Int) Int) diff --git a/test/regress/regress2/hash_sat_06_19.smt2 b/test/regress/regress2/hash_sat_06_19.smt2 index b565a4b57..d7f5ff7d4 100644 --- a/test/regress/regress2/hash_sat_06_19.smt2 +++ b/test/regress/regress2/hash_sat_06_19.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | MathSat group |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun hash_1 (Int) Int) diff --git a/test/regress/regress2/hash_sat_07_17.smt2 b/test/regress/regress2/hash_sat_07_17.smt2 index 0bb49801a..73220dd08 100644 --- a/test/regress/regress2/hash_sat_07_17.smt2 +++ b/test/regress/regress2/hash_sat_07_17.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | MathSat group |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun hash_1 (Int) Int) diff --git a/test/regress/regress2/hash_sat_09_09.smt2 b/test/regress/regress2/hash_sat_09_09.smt2 index 6dc26542e..5924973e9 100644 --- a/test/regress/regress2/hash_sat_09_09.smt2 +++ b/test/regress/regress2/hash_sat_09_09.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | MathSat group |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun hash_1 (Int) Int) diff --git a/test/regress/regress2/hash_sat_10_09.smt2 b/test/regress/regress2/hash_sat_10_09.smt2 index 20cff8b1b..0a60ed9b5 100644 --- a/test/regress/regress2/hash_sat_10_09.smt2 +++ b/test/regress/regress2/hash_sat_10_09.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | MathSat group |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "crafted") (set-info :status sat) (declare-fun hash_1 (Int) Int) diff --git a/test/regress/regress2/javafe.ast.StandardPrettyPrint.319_no_forall.smt2 b/test/regress/regress2/javafe.ast.StandardPrettyPrint.319_no_forall.smt2 index 9a737a3d1..6daa38e01 100644 --- a/test/regress/regress2/javafe.ast.StandardPrettyPrint.319_no_forall.smt2 +++ b/test/regress/regress2/javafe.ast.StandardPrettyPrint.319_no_forall.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/javafe.ast.WhileStmt.447_no_forall.smt2 b/test/regress/regress2/javafe.ast.WhileStmt.447_no_forall.smt2 index ff7c09997..da9800ca8 100644 --- a/test/regress/regress2/javafe.ast.WhileStmt.447_no_forall.smt2 +++ b/test/regress/regress2/javafe.ast.WhileStmt.447_no_forall.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/nl/nt-lemmas-bad.smt2 b/test/regress/regress2/nl/nt-lemmas-bad.smt2 index cea877c23..43a5f3d88 100644 --- a/test/regress/regress2/nl/nt-lemmas-bad.smt2 +++ b/test/regress/regress2/nl/nt-lemmas-bad.smt2 @@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun skoX () Real) diff --git a/test/regress/regress2/ooo.rf6.smt2 b/test/regress/regress2/ooo.rf6.smt2 index 4860a3428..63cebc50c 100644 --- a/test/regress/regress2/ooo.rf6.smt2 +++ b/test/regress/regress2/ooo.rf6.smt2 @@ -5,7 +5,7 @@ UCLID benchmark suite. See UCLID project: http://www.cs.cmu.edu/~uclid This benchmark was automatically translated into SMT-LIB format from CVC format using CVC Lite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun BOOOB_46_init_null_val () Int) diff --git a/test/regress/regress2/ooo.tag10.smt2 b/test/regress/regress2/ooo.tag10.smt2 index ef8e2244c..2d5cb3b37 100644 --- a/test/regress/regress2/ooo.tag10.smt2 +++ b/test/regress/regress2/ooo.tag10.smt2 @@ -5,7 +5,7 @@ UCLID benchmark suite. See UCLID project: http://www.cs.cmu.edu/~uclid This benchmark was automatically translated into SMT-LIB format from CVC format using CVC Lite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun Br1 () Int) diff --git a/test/regress/regress2/piVC_5581bd.smt2 b/test/regress/regress2/piVC_5581bd.smt2 index 78baeea84..aab556d69 100644 --- a/test/regress/regress2/piVC_5581bd.smt2 +++ b/test/regress/regress2/piVC_5581bd.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source |piVC|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun V_26 () Int) diff --git a/test/regress/regress2/quantifiers/AdditiveMethods_AdditiveMethods..ctor.smt2 b/test/regress/regress2/quantifiers/AdditiveMethods_AdditiveMethods..ctor.smt2 index bbd32d988..a8559a90a 100644 --- a/test/regress/regress2/quantifiers/AdditiveMethods_AdditiveMethods..ctor.smt2 +++ b/test/regress/regress2/quantifiers/AdditiveMethods_AdditiveMethods..ctor.smt2 @@ -3,7 +3,7 @@ Boogie/Spec# benchmarks. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun boolIff (Int Int) Int) diff --git a/test/regress/regress2/quantifiers/javafe.ast.ArrayInit.35.smt2 b/test/regress/regress2/quantifiers/javafe.ast.ArrayInit.35.smt2 index 811796bbf..dcdc41886 100644 --- a/test/regress/regress2/quantifiers/javafe.ast.ArrayInit.35.smt2 +++ b/test/regress/regress2/quantifiers/javafe.ast.ArrayInit.35.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/quantifiers/javafe.ast.StandardPrettyPrint.319.smt2 b/test/regress/regress2/quantifiers/javafe.ast.StandardPrettyPrint.319.smt2 index fd672bd3b..d608ce067 100644 --- a/test/regress/regress2/quantifiers/javafe.ast.StandardPrettyPrint.319.smt2 +++ b/test/regress/regress2/quantifiers/javafe.ast.StandardPrettyPrint.319.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/quantifiers/javafe.ast.WhileStmt.447.smt2 b/test/regress/regress2/quantifiers/javafe.ast.WhileStmt.447.smt2 index 9a5c07194..9a2eb411a 100644 --- a/test/regress/regress2/quantifiers/javafe.ast.WhileStmt.447.smt2 +++ b/test/regress/regress2/quantifiers/javafe.ast.WhileStmt.447.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/quantifiers/javafe.tc.CheckCompilationUnit.001.smt2 b/test/regress/regress2/quantifiers/javafe.tc.CheckCompilationUnit.001.smt2 index e0938975c..f932c5349 100644 --- a/test/regress/regress2/quantifiers/javafe.tc.CheckCompilationUnit.001.smt2 +++ b/test/regress/regress2/quantifiers/javafe.tc.CheckCompilationUnit.001.smt2 @@ -3,7 +3,7 @@ Simplify front end test suite. This benchmark was translated by Michal Moskal. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun L_102.5 () Int) diff --git a/test/regress/regress2/quantifiers/javafe.tc.FlowInsensitiveChecks.682.smt2 b/test/regress/regress2/quantifiers/javafe.tc.FlowInsensitiveChecks.682.smt2 index 2867e618f..a08a007c6 100644 --- a/test/regress/regress2/quantifiers/javafe.tc.FlowInsensitiveChecks.682.smt2 +++ b/test/regress/regress2/quantifiers/javafe.tc.FlowInsensitiveChecks.682.smt2 @@ -1,6 +1,6 @@ (set-logic AUFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/simplify.javafe.ast.ArrayInit.35_without_quantification2.smt2 b/test/regress/regress2/simplify.javafe.ast.ArrayInit.35_without_quantification2.smt2 index 6dc6318a4..4adf5e7cb 100644 --- a/test/regress/regress2/simplify.javafe.ast.ArrayInit.35_without_quantification2.smt2 +++ b/test/regress/regress2/simplify.javafe.ast.ArrayInit.35_without_quantification2.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | Simplify Theorem Prover Benchmark Suite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun true_term () Int) diff --git a/test/regress/regress2/strings/cmu-dis-0707-3.smt2 b/test/regress/regress2/strings/cmu-dis-0707-3.smt2 index 3bf47ed61..fcdcded39 100644 --- a/test/regress/regress2/strings/cmu-dis-0707-3.smt2 +++ b/test/regress/regress2/strings/cmu-dis-0707-3.smt2 @@ -1,7 +1,7 @@ -; COMMAND-LINE: --lang=smt2.0 ; EXPECT: sat (set-logic ALL_SUPPORTED) (set-info :status sat) +(set-info :smt-lib-version 2.6) (set-option :strings-exp true) (declare-fun value () String) (declare-fun name () String) @@ -11,12 +11,12 @@ (assert (not (not (= (ite (> (str.indexof value ":" 0) 0) 1 0) 0)))) (assert (not (= (ite (not (= (str.len value) 0)) 1 0) 0))) (assert (not (not (= (ite (str.contains value "'") 1 0) 0)))) -(assert (not (not (= (ite (str.contains value "\"") 1 0) 0)))) +(assert (not (not (= (ite (str.contains value "\\""") 1 0) 0)))) (assert (not (not (= (ite (str.contains value ">") 1 0) 0)))) (assert (not (not (= (ite (str.contains value "<") 1 0) 0)))) (assert (not (not (= (ite (str.contains value "&") 1 0) 0)))) (assert (not (not (= (ite (str.contains name "'") 1 0) 0)))) -(assert (not (not (= (ite (str.contains name "\"") 1 0) 0)))) +(assert (not (not (= (ite (str.contains name "\\""") 1 0) 0)))) (assert (not (not (= (ite (str.contains name ">") 1 0) 0)))) (assert (not (not (= (ite (str.contains name "<") 1 0) 0)))) (assert (not (not (= (ite (str.contains name "&") 1 0) 0)))) diff --git a/test/regress/regress2/strings/issue918.smt2 b/test/regress/regress2/strings/issue918.smt2 index 0843a1700..c335ca642 100644 --- a/test/regress/regress2/strings/issue918.smt2 +++ b/test/regress/regress2/strings/issue918.smt2 @@ -1,12 +1,9 @@ ; COMMAND-LINE: --strings-exp --re-elim ; EXPECT: sat -(set-info :smt-lib-version 2.5) +(set-info :smt-lib-version 2.6) (set-option :produce-models true) (set-logic UFDTSLIA) -(declare-datatypes () ( - (StringRotation (StringRotation$C_StringRotation (StringRotation$C_StringRotation$sr String))) - (StringRotation2 (StringRotation2$C_StringRotation2 (StringRotation2$C_StringRotation2$sr1 StringRotation) (StringRotation2$C_StringRotation2$sr2 StringRotation))) -) ) +(declare-datatypes ((StringRotation 0)(StringRotation2 0)) (((StringRotation$C_StringRotation (StringRotation$C_StringRotation$sr String)))((StringRotation2$C_StringRotation2 (StringRotation2$C_StringRotation2$sr1 StringRotation) (StringRotation2$C_StringRotation2$sr2 StringRotation))))) (define-fun f1005$isValid_string((x$$1008 String)) Bool true) (define-fun f1035$isValid_StringRotation((x$$1038 StringRotation)) Bool (and (f1005$isValid_string (StringRotation$C_StringRotation$sr x$$1038)) (or (or (or (= (StringRotation$C_StringRotation$sr x$$1038) "0 deg") (= (StringRotation$C_StringRotation$sr x$$1038) "90 deg")) (= (StringRotation$C_StringRotation$sr x$$1038) "180 deg")) (= (StringRotation$C_StringRotation$sr x$$1038) "270 deg")))) @@ -14,17 +11,7 @@ (declare-fun $OutSR$1356$3$1$() StringRotation2) (assert (f1121$isValid_StringRotation2 $OutSR$1356$3$1$)) -(assert (and (is-StringRotation2$C_StringRotation2 $OutSR$1356$3$1$) (and (and -(is-StringRotation$C_StringRotation (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (or -(str.in.re -(StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) -(re.++ (re.union (re.range "u" "~") (re.range " " "t") ) (re.union (re.range "K" "~") (re.range " " "J") ) (re.union (re.range "L" "~") (re.range " " "K") ) (re.union (re.range "y" "~") (re.range " " "x") ) (re.union (re.range "{" "~") (re.range " " "z") ) ) -) -(or -(str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) -(re.++ (re.union (re.range "s" "~") (re.range " " "r") ) (re.union (re.range "{" "~") (re.range " " "z") ) (re.union (re.range "u" "~") (re.range " " "t") ) ) ) +(assert (let ((_let_1 (re.* (re.union (re.range "\u{0}" "\u{9}") (re.range "\u{b}" "\u{c}") (re.range "\u{e}" "\u{7f}"))))) (let ((_let_2 (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$))) (let ((_let_3 (StringRotation$C_StringRotation$sr _let_2))) (let ((_let_4 (re.union (re.range "n" "~") (re.range " " "m")))) (let ((_let_5 (re.union (re.range "u" "~") (re.range " " "t")))) (let ((_let_6 (re.union (re.range "<" "~") (re.range " " ";")))) (let ((_let_7 (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$))) (let ((_let_8 (StringRotation$C_StringRotation$sr _let_7))) (let ((_let_9 (re.union (re.range "s" "~") (re.range " " "r")))) (let ((_let_10 (re.union (re.range "{" "~") (re.range " " "z")))) (and ((_ is StringRotation2$C_StringRotation2) $OutSR$1356$3$1$) (and (and ((_ is StringRotation$C_StringRotation) _let_7) (or (str.in_re _let_8 (re.++ _let_5 (re.union (re.range "K" "~") (re.range " " "J")) (re.union (re.range "L" "~") (re.range " " "K")) (re.union (re.range "y" "~") (re.range " " "x")) _let_10)) (or (str.in_re _let_8 (re.++ _let_9 _let_10 _let_5)) (or (str.in_re _let_8 _let_6) (or (str.in_re _let_8 (re.++ (re.union (re.range "&" "~") (re.range " " "%")) (re.range " " "~"))) (or (str.in_re _let_8 (re.++ (re.union (re.range "`" "~") (re.range " " "_")) _let_9 (re.union (re.range "1" "~") (re.range " " "0")) (re.union (re.range "_" "~") (re.range " " "^")))) (str.in_re _let_8 _let_1))))))) (and ((_ is StringRotation$C_StringRotation) _let_2) (or (str.in_re _let_3 (re.++ _let_6 (re.union (re.range "F" "~") (re.range " " "E")) _let_5 (re.union (re.range "P" "~") (re.range " " "O")))) (or (str.in_re _let_3 (re.union (re.range "E" "~") (re.range " " "D"))) (or (str.in_re _let_3 (re.++ (re.union (re.range "x" "~") (re.range " " "w")) _let_4 (re.union (re.range "d" "~") (re.range " " "c")) (re.union (re.range "]" "~") (re.range " " "\u{5c}")) (re.union (re.range "\u{5c}" "~") (re.range " " "[")))) (or (str.in_re _let_3 (re.++ (re.union (re.range ":" "~") (re.range " " "9")) (re.union (re.range "+" "~") (re.range " " "*")))) (or (str.in_re _let_3 (re.++ (re.union (re.range "." "~") (re.range " " "-")) _let_4 (re.union (re.range "|" "~") (re.range " " "{")))) (str.in_re _let_3 _let_1)))))))))))))))))))) -(or -(str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.union (re.range "<" "~") (re.range " " ";") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "&" "~") (re.range " " "%") ) (re.range " " "~") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "`" "~") (re.range " " "_") ) (re.union (re.range "s" "~") (re.range " " "r") ) (re.union (re.range "1" "~") (re.range " " "0") ) (re.union (re.range "_" "~") (re.range " " "^") ) ) ) (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.* (re.union (re.range "\x00" "\x09") (re.range "\x0B" "\x0C") (re.range "\x0E" "\x7F") ) ) ))))))) (and (is-StringRotation$C_StringRotation (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "<" "~") (re.range " " ";") ) (re.union (re.range "F" "~") (re.range " " "E") ) (re.union (re.range "u" "~") (re.range " " "t") ) (re.union (re.range "P" "~") (re.range " " "O") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.union (re.range "E" "~") (re.range " " "D") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "x" "~") (re.range " " "w") ) (re.union (re.range "n" "~") (re.range " " "m") ) (re.union (re.range "d" "~") (re.range " " "c") ) (re.union (re.range "]" "~") (re.range " " "\\") ) (re.union (re.range "\\" "~") (re.range " " "[") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range ":" "~") (re.range " " "9") ) (re.union (re.range "+" "~") (re.range " " "*") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "." "~") (re.range " " "-") ) (re.union (re.range "n" "~") (re.range " " "m") ) (re.union (re.range "|" "~") (re.range " " "{") ) ) ) (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.* (re.union (re.range "\x00" "\x09") (re.range "\x0B" "\x0C") (re.range "\x0E" "\x7F") ) ) )))))))))) (check-sat) diff --git a/test/regress/regress3/arith_prp-13-24.smt2 b/test/regress/regress3/arith_prp-13-24.smt2 index ffb7fcb0f..9b2b164fd 100644 --- a/test/regress/regress3/arith_prp-13-24.smt2 +++ b/test/regress/regress3/arith_prp-13-24.smt2 @@ -8,7 +8,7 @@ The logic is changed to QF_LIA. The category is set as industrial. The status (except 'large' cases) is assigned according to the 'outfile' on http://www.nec-labs.com/~fsoft/bench.html. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun i1430 () Int) diff --git a/test/regress/regress3/lpsat-goal-9.smt2 b/test/regress/regress3/lpsat-goal-9.smt2 index d71fc1340..eb26878ab 100644 --- a/test/regress/regress3/lpsat-goal-9.smt2 +++ b/test/regress/regress3/lpsat-goal-9.smt2 @@ -7,7 +7,7 @@ This benchmark was automatically translated into SMT-LIB format from CVC format using CVC Lite |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun cvclZero () Int) diff --git a/test/regress/regress3/specsharp-WindowsCard.15.RTE.Terminate_System.Int32.smt2 b/test/regress/regress3/specsharp-WindowsCard.15.RTE.Terminate_System.Int32.smt2 index 7be432dbf..67395e91a 100644 --- a/test/regress/regress3/specsharp-WindowsCard.15.RTE.Terminate_System.Int32.smt2 +++ b/test/regress/regress3/specsharp-WindowsCard.15.RTE.Terminate_System.Int32.smt2 @@ -2,7 +2,7 @@ (set-info :source |
Spec# benchmarks. Contributed by Leonardo de Moura and Michal Moskal.
|) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun x (Int Int) Int) diff --git a/test/regress/regress4/bug337.smt2 b/test/regress/regress4/bug337.smt2 index b7a564a60..0bae96dd1 100644 --- a/test/regress/regress4/bug337.smt2 +++ b/test/regress/regress4/bug337.smt2 @@ -4,7 +4,7 @@ Unbounded version of the queue lock algorithm. |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status sat) (declare-fun x_0 () Int) diff --git a/test/regress/regress4/bug396.smt2 b/test/regress/regress4/bug396.smt2 index 8e93cf447..639d4f7eb 100644 --- a/test/regress/regress4/bug396.smt2 +++ b/test/regress/regress4/bug396.smt2 @@ -11,7 +11,7 @@ ; EXPECT: unsat ;(set-option :produce-unsat-cores true) (set-option :print-success false) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) ;(set-option :produce-models true) (set-logic ALL_SUPPORTED) ; done setting options diff --git a/test/regress/regress4/miplib-pp08a-3000.smt2 b/test/regress/regress4/miplib-pp08a-3000.smt2 index edd77a9d1..ec420a8be 100644 --- a/test/regress/regress4/miplib-pp08a-3000.smt2 +++ b/test/regress/regress4/miplib-pp08a-3000.smt2 @@ -6,7 +6,7 @@ Relaxation of the Mixed-Integer Programming optimization problem pp08a from the MIPLIB (http://miplib.zib.de/) by Enric Rodriguez-Carbonell (erodri@lsi.upc.edu) |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun tmp75 () Real) diff --git a/test/regress/regress4/xs-11-20-5-2-5-3.smt2 b/test/regress/regress4/xs-11-20-5-2-5-3.smt2 index bdf0d25ab..f5f75a641 100644 --- a/test/regress/regress4/xs-11-20-5-2-5-3.smt2 +++ b/test/regress/regress4/xs-11-20-5-2-5-3.smt2 @@ -1,6 +1,6 @@ (set-logic QF_UFLIA) (set-info :source | MathSat group |) -(set-info :smt-lib-version 2.0) +(set-info :smt-lib-version 2.6) (set-info :category "industrial") (set-info :status unsat) (declare-fun fmt1 () Int) |