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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2019-12-05 09:19:56 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-05 09:19:56 -0600 |
| commit | f17b72fcdb535a5c06620900d2c35d2709abe968 (patch) | |
| tree | 408a48f718858c3623afbe1d8b99cab79cedaf35 /test/regress/regress2 | |
| parent | 97c2553d0b0535bd47517f755897c441e223568e (diff) | |
Refactor mode options for Unif+PI (#3531)
Diffstat (limited to 'test/regress/regress2')
| -rw-r--r-- | test/regress/regress2/sygus/cegisunif-depth1-bv.sy | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/regress/regress2/sygus/cegisunif-depth1-bv.sy b/test/regress/regress2/sygus/cegisunif-depth1-bv.sy index 4b0cefcda..6b647b77d 100644 --- a/test/regress/regress2/sygus/cegisunif-depth1-bv.sy +++ b/test/regress/regress2/sygus/cegisunif-depth1-bv.sy @@ -1,5 +1,5 @@ ; EXPECT: unsat -; COMMAND-LINE: --sygus-unif --sygus-out=status +; COMMAND-LINE: --sygus-unif-pi=complete --sygus-out=status (set-logic BV) (synth-fun f ((x (BitVec 64)) (y (BitVec 64))) (BitVec 64) |