Remove SMT-LIB 2.5 and 2.0 support. (#6068)

This commit removes parser and printer support for old SMT-LIB standards and also converts all regression tests to 2.6.
author: Mathias Preiner <mathias.preiner@gmail.com> 2021-03-05 16:17:15 -0800
committer: GitHub <noreply@github.com> 2021-03-06 00:17:15 +0000
commit: c6fffe4fd328401f7f7e0757303e8dea5f6c14a4 (patch)
tree: 84bbb3f44fa7ffbeba0c0baf9b7b22f036d2e9f4 /test/regress/regress1
parent: 555e4b0b6b10e9170676c0a3ef9b778322f3327f (diff)
71 files changed, 128 insertions, 159 deletions
diff --git a/test/regress/regress1/arith/bug716.0.smt2 b/test/regress/regress1/arith/bug716.0.smt2
index dd2501bbb..9e05e8b3d 100644
--- a/test/regress/regress1/arith/bug716.0.smt2
+++ b/test/regress/regress1/arith/bug716.0.smt2
@@ -7,7 +7,7 @@
 (set-logic AUFBVDTLIRA)
 ;; produced by cvc4_15.drv ;;
 (set-info :source |VC generated by SPARK 2014|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category industrial)
 (set-info :status unknown)
 ;;; generated by SMT-LIB2 driver
diff --git a/test/regress/regress1/arith/div.03.smt2 b/test/regress/regress1/arith/div.03.smt2
index 8beef7a69..51568b706 100644
--- a/test/regress/regress1/arith/div.03.smt2
+++ b/test/regress/regress1/arith/div.03.smt2
@@ -1,6 +1,6 @@
 ; EXPECT: unsat
 (set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status unsat)
 (declare-fun x () Int)
 (declare-fun n () Int)
diff --git a/test/regress/regress1/arith/div.06.smt2 b/test/regress/regress1/arith/div.06.smt2
index 45d687cab..b6a72d36f 100644
--- a/test/regress/regress1/arith/div.06.smt2
+++ b/test/regress/regress1/arith/div.06.smt2
@@ -1,7 +1,7 @@
 ; COMMAND-LINE: -q
 ; EXPECT: sat
 (set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status sat)
 (declare-fun x () Real)
 (declare-fun y () Real)
diff --git a/test/regress/regress1/arith/div.08.smt2 b/test/regress/regress1/arith/div.08.smt2
index 0b0d73ac1..d43110947 100644
--- a/test/regress/regress1/arith/div.08.smt2
+++ b/test/regress/regress1/arith/div.08.smt2
@@ -1,5 +1,5 @@
 (set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status unsat)
 (declare-fun n () Int)
 
diff --git a/test/regress/regress1/arith/mod.02.smt2 b/test/regress/regress1/arith/mod.02.smt2
index ee4333ea5..770de4c45 100644
--- a/test/regress/regress1/arith/mod.02.smt2
+++ b/test/regress/regress1/arith/mod.02.smt2
@@ -1,6 +1,6 @@
 ; EXPECT: unsat
 (set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status unsat)
 (declare-fun n () Int)
 
diff --git a/test/regress/regress1/arith/mod.03.smt2 b/test/regress/regress1/arith/mod.03.smt2
index 583c72a93..58dbd2319 100644
--- a/test/regress/regress1/arith/mod.03.smt2
+++ b/test/regress/regress1/arith/mod.03.smt2
@@ -1,7 +1,7 @@
 ; COMMAND-LINE: -q
 ; EXPECT: sat
 (set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status sat)
 (declare-fun n () Int)
 (declare-fun x () Int)
diff --git a/test/regress/regress1/arith/problem__003.smt2 b/test/regress/regress1/arith/problem__003.smt2
index 7af727e2a..fe177362c 100644
--- a/test/regress/regress1/arith/problem__003.smt2
+++ b/test/regress/regress1/arith/problem__003.smt2
@@ -3,7 +3,7 @@
 Alberto Griggio
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (declare-fun x0 () Int)
diff --git a/test/regress/regress1/aufbv/bug580.smt2 b/test/regress/regress1/aufbv/bug580.smt2
index 2f2074385..074c7523a 100644
--- a/test/regress/regress1/aufbv/bug580.smt2
+++ b/test/regress/regress1/aufbv/bug580.smt2
@@ -1,5 +1,5 @@
 (set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (set-logic QF_AUFBV)
diff --git a/test/regress/regress1/auflia/bug330.smt2 b/test/regress/regress1/auflia/bug330.smt2
index ce787e2e7..ada1fd8d5 100644
--- a/test/regress/regress1/auflia/bug330.smt2
+++ b/test/regress/regress1/auflia/bug330.smt2
@@ -6,7 +6,7 @@ Barrett at barrett@cs.stanford.edu for more information.
 This benchmark was automatically translated into SMT-LIB format from
 CVC format using CVC Lite
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (set-info :difficulty | 0 |)
diff --git a/test/regress/regress1/bug512.smt2 b/test/regress/regress1/bug512.smt2
index 1c8a0626a..6932e8d5d 100644
--- a/test/regress/regress1/bug512.smt2
+++ b/test/regress/regress1/bug512.smt2
@@ -3,7 +3,7 @@
 ; EXPECT: (:reason-unknown incomplete)
 ; EXPECT: unsat
 (set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 ;(set-option :AUTO_CONFIG false)
 ;(set-option :MODEL_HIDE_UNUSED_PARTITIONS false)
 ;(set-option :MODEL_V2 true)
diff --git a/test/regress/regress1/bug521.smt2 b/test/regress/regress1/bug521.smt2
index 8f840a1f6..73153e71b 100644
--- a/test/regress/regress1/bug521.smt2
+++ b/test/regress/regress1/bug521.smt2
@@ -1,7 +1,7 @@
 ;(set-option :produce-unsat-cores true)
 (set-option :incremental true)
 (set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status sat)
 (set-option :produce-models true)
 (set-logic ALL_SUPPORTED)
diff --git a/test/regress/regress1/bug590.smt2 b/test/regress/regress1/bug590.smt2
index d50024268..68a2fb9a3 100644
--- a/test/regress/regress1/bug590.smt2
+++ b/test/regress/regress1/bug590.smt2
@@ -4,7 +4,7 @@
 (set-logic ALL)
 (set-option :strings-exp true)
 (set-option :produce-models true)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status unknown)
 
 (declare-fun text () String)
@@ -21,7 +21,7 @@
 (assert (= html_escape_table 
     (store (store (store (store (store ((as const (Array String String)) "A") 
     "&" "&amp;") 
-    "\"" "&quot;")
+    "\\""" "&quot;")
     "'" "&apos;") 
     ">" "&gt;") 
     "<" "&lt;")))
@@ -29,7 +29,7 @@
 (assert (= html_escape_table_keys
     (store (store (store (store (store ((as const (Array Int String)) "B")
     0 "&")
-    1 "\"")
+    1 "\\""")
     2 "'")
     3 ">")
     4 "<"))) 
diff --git a/test/regress/regress1/bug800.smt2 b/test/regress/regress1/bug800.smt2
index d36f62b16..b62be95bd 100644
--- a/test/regress/regress1/bug800.smt2
+++ b/test/regress/regress1/bug800.smt2
@@ -3,7 +3,7 @@
 ; EXPECT: sat
 (set-logic QF_UFLRA)
 (set-info :source |CPAchecker with bounded model checking on SV-COMP14 program using MathSAT5, submitted by Philipp Wendler, http://cpachecker.sosy-lab.org|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 
 
diff --git a/test/regress/regress1/bv/decision-weight00.smt2 b/test/regress/regress1/bv/decision-weight00.smt2
index be52810e0..5d851f0d4 100644
--- a/test/regress/regress1/bv/decision-weight00.smt2
+++ b/test/regress/regress1/bv/decision-weight00.smt2
@@ -5,7 +5,7 @@
  Patrice Godefroid, SAGE (systematic dynamic test generation)
  For more information: http://research.microsoft.com/en-us/um/people/pg/public_psfiles/ndss2008.pdf
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unknown)
 (declare-fun x () (_ BitVec 32))
diff --git a/test/regress/regress1/bvdiv2.smt2 b/test/regress/regress1/bvdiv2.smt2
index 7a8fc3753..67d583c76 100644
--- a/test/regress/regress1/bvdiv2.smt2
+++ b/test/regress/regress1/bvdiv2.smt2
@@ -1,5 +1,5 @@
 (set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-fun x0 () (_ BitVec 10))
diff --git a/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2 b/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2
index f2a5b81c8..f7c13722b 100644
--- a/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2
+++ b/test/regress/regress1/datatypes/issue-variant-dt-zero.smt2
@@ -1,16 +1,9 @@
 ; COMMAND-LINE: --fmf-fun-rlv --no-check-models
 ; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String)))
-                       (a1(c1$0)(c1$1)(c1$2))
-                       (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool)))
-                       (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String)))
-                       (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2))
-                       (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6))
-                       (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6))
-                       (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool)))))
 (define-funs-rec ((f0((v0 a6))a4))
                   (c4$2))
 (check-sat)
diff --git a/test/regress/regress1/datatypes/issue3266-small.smt2 b/test/regress/regress1/datatypes/issue3266-small.smt2
index c57268cc9..d4b09e5ef 100644
--- a/test/regress/regress1/datatypes/issue3266-small.smt2
+++ b/test/regress/regress1/datatypes/issue3266-small.smt2
@@ -5,10 +5,10 @@
 ; EXPECT: sat
 ; EXPECT: sat
 ; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a8)(c0$3$1 Int))(c0$4(c0$4$0 a5)(c0$4$1 a6))(c0$5)(c0$6)(c0$7)(c0$8))(a1(c1$0)(c1$1(c1$1$0 a4)(c1$1$1 Bool)(c1$1$2 a6)(c1$1$3 a4)(c1$1$4 ab)(c1$1$5 Int)(c1$1$6 a0))(c1$2)(c1$3)(c1$4)(c1$5(c1$5$0 a7))(c1$6(c1$6$0 String)(c1$6$1 a4)(c1$6$2 a4)(c1$6$3 a0))(c1$7))(a2(c2$0)(c2$1(c2$1$0 aa)(c2$1$1 aa)(c2$1$2 a1)(c2$1$3 a0)(c2$1$4 a0)(c2$1$5 a0)(c2$1$6 a9))(c2$2(c2$2$0 a5)(c2$2$1 ab))(c2$3(c2$3$0 Bool)(c2$3$1 a7)(c2$3$2 a3)(c2$3$3 Bool)(c2$3$4 a0)(c2$3$5 String))(c2$4))(a3(c3$0(c3$0$0 a7))(c3$1)(c3$2)(c3$3)(c3$4)(c3$5)(c3$6)(c3$7)(c3$8)(c3$9)(c3$a)(c3$b)(c3$c))(a4(c4$0(c4$0$0 a2)(c4$0$1 a1)(c4$0$2 Bool)(c4$0$3 String)(c4$0$4 a3)(c4$0$5 Int)(c4$0$6 a2)))(a5(c5$0)(c5$1)(c5$2(c5$2$0 String))(c5$3)(c5$4)(c5$5)(c5$6(c5$6$0 a0)(c5$6$1 a6)(c5$6$2 a3)(c5$6$3 a3)(c5$6$4 a9))(c5$7))(a6(c6$0)(c6$1(c6$1$0 a7))(c6$2)(c6$3)(c6$4(c6$4$0 a7)(c6$4$1 a3)(c6$4$2 a4))(c6$5(c6$5$0 a9)(c6$5$1 a9)(c6$5$2 a7)(c6$5$3 a6)(c6$5$4 ab)(c6$5$5 a5)(c6$5$6 a3)(c6$5$7 aa))(c6$6)(c6$7)(c6$8)(c6$9)(c6$a)(c6$b)(c6$c))(a7(c7$0)(c7$1)(c7$2)(c7$3(c7$3$0 a8)(c7$3$1 Bool)(c7$3$2 Int)(c7$3$3 a5)(c7$3$4 a8))(c7$4)(c7$5)(c7$6)(c7$7)(c7$8(c7$8$0 a5)(c7$8$1 a1)))(a8(c8$0(c8$0$0 a6)(c8$0$1 ab)(c8$0$2 ab)(c8$0$3 a1)(c8$0$4 Bool))(c8$1(c8$1$0 a4)(c8$1$1 Bool)(c8$1$2 a2)(c8$1$3 String)(c8$1$4 Bool)))(a9(c9$0(c9$0$0 String))(c9$1(c9$1$0 String)(c9$1$1 ab))(c9$2(c9$2$0 a5)(c9$2$1 a9))(c9$3(c9$3$0 String)(c9$3$1 a8)(c9$3$2 a6))(c9$4)(c9$5))(aa(ca$0(ca$0$0 String)(ca$0$1 a3)(ca$0$2 a9)(ca$0$3 a3)(ca$0$4 Bool)(ca$0$5 a1)(ca$0$6 a1)(ca$0$7 a4))(ca$1)(ca$2(ca$2$0 a4)(ca$2$1 String)(ca$2$2 aa)(ca$2$3 ab)))(ab(cb$0(cb$0$0 a5)(cb$0$1 a2)(cb$0$2 a3)(cb$0$3 aa)(cb$0$4 Bool))(cb$1(cb$1$0 a0))(cb$2)(cb$3)(cb$4)(cb$5)(cb$6)(cb$7(cb$7$0 String)(cb$7$1 a0)(cb$7$2 a7)(cb$7$3 ab)(cb$7$4 aa)(cb$7$5 a8))(cb$8))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)(a8 0)(a9 0)(aa 0)(ab 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a8) (c0$3$1 Int)) (c0$4 (c0$4$0 a5) (c0$4$1 a6)) (c0$5) (c0$6) (c0$7) (c0$8))((c1$0) (c1$1 (c1$1$0 a4) (c1$1$1 Bool) (c1$1$2 a6) (c1$1$3 a4) (c1$1$4 ab) (c1$1$5 Int) (c1$1$6 a0)) (c1$2) (c1$3) (c1$4) (c1$5 (c1$5$0 a7)) (c1$6 (c1$6$0 String) (c1$6$1 a4) (c1$6$2 a4) (c1$6$3 a0)) (c1$7))((c2$0) (c2$1 (c2$1$0 aa) (c2$1$1 aa) (c2$1$2 a1) (c2$1$3 a0) (c2$1$4 a0) (c2$1$5 a0) (c2$1$6 a9)) (c2$2 (c2$2$0 a5) (c2$2$1 ab)) (c2$3 (c2$3$0 Bool) (c2$3$1 a7) (c2$3$2 a3) (c2$3$3 Bool) (c2$3$4 a0) (c2$3$5 String)) (c2$4))((c3$0 (c3$0$0 a7)) (c3$1) (c3$2) (c3$3) (c3$4) (c3$5) (c3$6) (c3$7) (c3$8) (c3$9) (c3$a) (c3$b) (c3$c))((c4$0 (c4$0$0 a2) (c4$0$1 a1) (c4$0$2 Bool) (c4$0$3 String) (c4$0$4 a3) (c4$0$5 Int) (c4$0$6 a2)))((c5$0) (c5$1) (c5$2 (c5$2$0 String)) (c5$3) (c5$4) (c5$5) (c5$6 (c5$6$0 a0) (c5$6$1 a6) (c5$6$2 a3) (c5$6$3 a3) (c5$6$4 a9)) (c5$7))((c6$0) (c6$1 (c6$1$0 a7)) (c6$2) (c6$3) (c6$4 (c6$4$0 a7) (c6$4$1 a3) (c6$4$2 a4)) (c6$5 (c6$5$0 a9) (c6$5$1 a9) (c6$5$2 a7) (c6$5$3 a6) (c6$5$4 ab) (c6$5$5 a5) (c6$5$6 a3) (c6$5$7 aa)) (c6$6) (c6$7) (c6$8) (c6$9) (c6$a) (c6$b) (c6$c))((c7$0) (c7$1) (c7$2) (c7$3 (c7$3$0 a8) (c7$3$1 Bool) (c7$3$2 Int) (c7$3$3 a5) (c7$3$4 a8)) (c7$4) (c7$5) (c7$6) (c7$7) (c7$8 (c7$8$0 a5) (c7$8$1 a1)))((c8$0 (c8$0$0 a6) (c8$0$1 ab) (c8$0$2 ab) (c8$0$3 a1) (c8$0$4 Bool)) (c8$1 (c8$1$0 a4) (c8$1$1 Bool) (c8$1$2 a2) (c8$1$3 String) (c8$1$4 Bool)))((c9$0 (c9$0$0 String)) (c9$1 (c9$1$0 String) (c9$1$1 ab)) (c9$2 (c9$2$0 a5) (c9$2$1 a9)) (c9$3 (c9$3$0 String) (c9$3$1 a8) (c9$3$2 a6)) (c9$4) (c9$5))((ca$0 (ca$0$0 String) (ca$0$1 a3) (ca$0$2 a9) (ca$0$3 a3) (ca$0$4 Bool) (ca$0$5 a1) (ca$0$6 a1) (ca$0$7 a4)) (ca$1) (ca$2 (ca$2$0 a4) (ca$2$1 String) (ca$2$2 aa) (ca$2$3 ab)))((cb$0 (cb$0$0 a5) (cb$0$1 a2) (cb$0$2 a3) (cb$0$3 aa) (cb$0$4 Bool)) (cb$1 (cb$1$0 a0)) (cb$2) (cb$3) (cb$4) (cb$5) (cb$6) (cb$7 (cb$7$0 String) (cb$7$1 a0) (cb$7$2 a7) (cb$7$3 ab) (cb$7$4 aa) (cb$7$5 a8)) (cb$8))))
 (push 1)
 (declare-fun v0() a0)
 (push 1)
diff --git a/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2 b/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2
index cfb036f16..963e270a6 100644
--- a/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2
+++ b/test/regress/regress1/decision/quant-Arrays_Q1-noinfer.smt2
@@ -6,7 +6,7 @@
   Boogie/Spec# benchmarks.
   This benchmark was translated by Michal Moskal.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun InRange (Int Int) Bool)
diff --git a/test/regress/regress1/fmf/issue916-fmf-or.smt2 b/test/regress/regress1/fmf/issue916-fmf-or.smt2
index 0c51e39af..479769188 100644
--- a/test/regress/regress1/fmf/issue916-fmf-or.smt2
+++ b/test/regress/regress1/fmf/issue916-fmf-or.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: sat
 
 (set-logic UFDTLIA)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 
 (define-funs-rec
   (
@@ -22,8 +22,8 @@
   )
 )
 
-(declare-datatypes (T) ( (List (Nil) (Cstr (head T) (tail List) ) ) ) )
-(declare-datatypes (T S) ( (Pair (Pair (first T) (second S)) ) ) )
+(declare-datatypes ((List 1)) ((par (T)((Nil) (Cstr (head T) (tail (List T)))))))
+(declare-datatypes ((Pair 2)) ((par (T S)((Pair (first T) (second S))))))
 
 (define-funs-rec
   (
diff --git a/test/regress/regress1/fmf/refcount24.cvc.smt2 b/test/regress/regress1/fmf/refcount24.cvc.smt2
index 2aaa28a3a..510e5c4db 100644
--- a/test/regress/regress1/fmf/refcount24.cvc.smt2
+++ b/test/regress/regress1/fmf/refcount24.cvc.smt2
@@ -1,15 +1,11 @@
 ; COMMAND-LINE: --finite-model-find -q
 ; EXPECT: sat
 (set-logic ALL_SUPPORTED)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "unknown")
 (set-info :status sat)
-(declare-datatypes () 
-((UNIT  (Unit))
-))
-(declare-datatypes () 
-((BOOL  (Truth)  (Falsity))
-))
+(declare-datatype UNIT ((Unit)))
+(declare-datatype BOOL ((Truth)  (Falsity)))
 (declare-sort resource$type 0)
 (declare-sort process$type 0)
 (declare-fun null () resource$type)
diff --git a/test/regress/regress1/fp/rti_3_5_bug_report.smt2 b/test/regress/regress1/fp/rti_3_5_bug_report.smt2
index 5a52ffcc9..3e94e6e05 100644
--- a/test/regress/regress1/fp/rti_3_5_bug_report.smt2
+++ b/test/regress/regress1/fp/rti_3_5_bug_report.smt2
@@ -1,20 +1,20 @@
-; REQUIRES: symfpu
-; COMMAND-LINE: --fp-exp
-; EXPECT: unsat
-
-(set-logic FP)
-(set-info :source |Written by Mathias Preiner for issue #2932|)
-(set-info :smt-lib-version 2.5)
-(set-info :category crafted)
-(set-info :status unsat)
-
-(define-sort FP () (_ FloatingPoint 3 5))
-(declare-const t FP)
-(assert
-  (distinct
-    (= t (fp.roundToIntegral RNA t))  
-    (exists ((x FP)) (= (fp.roundToIntegral RNA x) t)) 
- )
-)
-(check-sat)
-(exit)
+; REQUIRES: symfpu
+; COMMAND-LINE: --fp-exp
+; EXPECT: unsat
+
+(set-logic FP)
+(set-info :source |Written by Mathias Preiner for issue #2932|)
+(set-info :smt-lib-version 2.6)
+(set-info :category crafted)
+(set-info :status unsat)
+
+(define-sort FP () (_ FloatingPoint 3 5))
+(declare-const t FP)
+(assert
+  (distinct
+    (= t (fp.roundToIntegral RNA t))  
+    (exists ((x FP)) (= (fp.roundToIntegral RNA x) t)) 
+ )
+)
+(check-sat)
+(exit)
diff --git a/test/regress/regress1/gensys_brn001.smt2 b/test/regress/regress1/gensys_brn001.smt2
index f3cc3c725..dab29c4b2 100644
--- a/test/regress/regress1/gensys_brn001.smt2
+++ b/test/regress/regress1/gensys_brn001.smt2
@@ -3,7 +3,7 @@
 http://www.cs.bham.ac.uk/~vxs/quasigroups/benchmark/
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status sat)
 (declare-sort U 0)
diff --git a/test/regress/regress1/nl/bug698.smt2 b/test/regress/regress1/nl/bug698.smt2
index ffb1eead2..f24d05372 100644
--- a/test/regress/regress1/nl/bug698.smt2
+++ b/test/regress/regress1/nl/bug698.smt2
@@ -1,6 +1,6 @@
 ; COMMAND-LINE: --incremental --nl-ext --fmf-fun-rlv --no-check-models
 (set-logic UFNIA)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 
 ; EXPECT: sat
 (declare-fun fixedAdd() Int)
diff --git a/test/regress/regress1/nl/metitarski-1025.smt2 b/test/regress/regress1/nl/metitarski-1025.smt2
index 73a132350..3fbf9cb77 100644
--- a/test/regress/regress1/nl/metitarski-1025.smt2
+++ b/test/regress/regress1/nl/metitarski-1025.smt2
@@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB.
 
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status sat)
 (declare-fun skoCOSS () Real)
diff --git a/test/regress/regress1/nl/metitarski-3-4.smt2 b/test/regress/regress1/nl/metitarski-3-4.smt2
index 3a1e794cc..f26640f49 100644
--- a/test/regress/regress1/nl/metitarski-3-4.smt2
+++ b/test/regress/regress1/nl/metitarski-3-4.smt2
@@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB.
 
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status sat)
 (declare-fun skoX () Real)
diff --git a/test/regress/regress1/nl/metitarski_3_4_2e.smt2 b/test/regress/regress1/nl/metitarski_3_4_2e.smt2
index 3f12ec34b..07efc3d32 100644
--- a/test/regress/regress1/nl/metitarski_3_4_2e.smt2
+++ b/test/regress/regress1/nl/metitarski_3_4_2e.smt2
@@ -19,7 +19,7 @@ Submitted by Dejan Jovanovic for SMT-LIB.
 
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status sat)
 (declare-fun skoX () Real)
diff --git a/test/regress/regress1/nl/nl-help-unsat-quant.smt2 b/test/regress/regress1/nl/nl-help-unsat-quant.smt2
index f2f7667c8..d0acca99d 100644
--- a/test/regress/regress1/nl/nl-help-unsat-quant.smt2
+++ b/test/regress/regress1/nl/nl-help-unsat-quant.smt2
@@ -3,7 +3,7 @@
 (set-logic UFNIA)
 (set-info :status unsat)
 (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011.  Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (declare-sort S1 0)
 (declare-sort S2 0)
diff --git a/test/regress/regress1/nl/nl-unk-quant.smt2 b/test/regress/regress1/nl/nl-unk-quant.smt2
index bb5cd43df..64cc419d7 100644
--- a/test/regress/regress1/nl/nl-unk-quant.smt2
+++ b/test/regress/regress1/nl/nl-unk-quant.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: unsat
 (set-logic UFNIA)
 (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011.  Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort S1 0)
diff --git a/test/regress/regress1/nl/poly-1025.smt2 b/test/regress/regress1/nl/poly-1025.smt2
index 482696532..2fb918e3c 100644
--- a/test/regress/regress1/nl/poly-1025.smt2
+++ b/test/regress/regress1/nl/poly-1025.smt2
@@ -18,7 +18,7 @@ Submitted by Dejan Jovanovic for SMT-LIB.
 
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status sat)
 (declare-fun skoX () Real)
diff --git a/test/regress/regress1/nl/quant-nl.smt2 b/test/regress/regress1/nl/quant-nl.smt2
index 7d251ab7d..f47023e99 100644
--- a/test/regress/regress1/nl/quant-nl.smt2
+++ b/test/regress/regress1/nl/quant-nl.smt2
@@ -3,7 +3,7 @@
 (set-logic UFNIA)
 (set-info :status unsat)
 (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011.  Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (declare-sort S1 0)
 (declare-sort S2 0)
diff --git a/test/regress/regress1/proof00.smt2 b/test/regress/regress1/proof00.smt2
index 1b7e7b8dd..faae38923 100644
--- a/test/regress/regress1/proof00.smt2
+++ b/test/regress/regress1/proof00.smt2
@@ -7,7 +7,7 @@ CADE ATP System competition. See http://www.cs.miami.edu/~tptp/CASC
 This benchmark was obtained by trying to find a finite model of a first-order 
 formula (Albert Oliveras).
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-sort U 0)
diff --git a/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2 b/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2
index 670dcc006..ed5bf2a3d 100644
--- a/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2
+++ b/test/regress/regress1/quantifiers/AdditiveMethods_OwnedResults.Mz.smt2
@@ -3,7 +3,7 @@
   Boogie/Spec# benchmarks.
   This benchmark was translated by Michal Moskal.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun boolIff (Int Int) Int)
diff --git a/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2 b/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2
index 3398f5f84..12a17cfe8 100644
--- a/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2
+++ b/test/regress/regress1/quantifiers/Arrays_Q1-noinfer.smt2
@@ -3,7 +3,7 @@
   Boogie/Spec# benchmarks.
   This benchmark was translated by Michal Moskal.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun InRange (Int Int) Bool)
diff --git a/test/regress/regress1/quantifiers/array-unsat-simp3.smt2 b/test/regress/regress1/quantifiers/array-unsat-simp3.smt2
index 9dade2073..1666102e5 100644
--- a/test/regress/regress1/quantifiers/array-unsat-simp3.smt2
+++ b/test/regress/regress1/quantifiers/array-unsat-simp3.smt2
@@ -1,7 +1,7 @@
 ; COMMAND-LINE: --full-saturate-quant
 ; EXPECT: unsat
 (set-logic AUFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-sort Index 0)
diff --git a/test/regress/regress1/quantifiers/bignum_quant.smt2 b/test/regress/regress1/quantifiers/bignum_quant.smt2
index 74b08a2da..3e4cad64e 100644
--- a/test/regress/regress1/quantifiers/bignum_quant.smt2
+++ b/test/regress/regress1/quantifiers/bignum_quant.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIA)
 (set-info :source | SMT-COMP'06 organizers |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "check")
 (set-info :status unsat)
 (set-info :notes |This benchmark is designed to check if the DP supports bignumbers.|)
diff --git a/test/regress/regress1/quantifiers/bug802.smt2 b/test/regress/regress1/quantifiers/bug802.smt2
index 57da8510e..d5d0b0d7d 100644
--- a/test/regress/regress1/quantifiers/bug802.smt2
+++ b/test/regress/regress1/quantifiers/bug802.smt2
@@ -4,7 +4,7 @@ Hardware fixpoint check problems.
 These benchmarks stem from an evaluation described in Wintersteiger, Hamadi, de Moura: Efficiently solving quantified bit-vector formulas, FMSD 42(1), 2013.
 The hardware models that were used are from the VCEGAR benchmark suite (see www.cprover.org/hardware/).
  |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (assert (forall ((Verilog__main.reset_64_0 Bool)) (forall ((Verilog__main.rst_64_0 Bool)) (forall ((Verilog__main.usb_rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_0 Bool)) (forall ((Verilog__main.clk_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_0 Bool)) (forall ((Verilog__main.phy_tx_mode_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_0 Bool)) (forall ((Verilog__main.txdp_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_0 Bool)) (forall ((Verilog__main.txdn_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_0 Bool)) (forall ((Verilog__main.txoe_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_0 Bool)) (forall ((Verilog__main.TxValid_i_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_0 Bool)) (forall ((Verilog__main.TxReady_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_0 Bool)) (forall ((Verilog__main.rxd_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_0 Bool)) (forall ((Verilog__main.rxdp_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_0 Bool)) (forall ((Verilog__main.rxdn_64_0 Bool)) (forall ((Verilog__main.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_0 Bool)) (forall ((Verilog__main.RxActive_o_64_0 Bool)) (forall ((Verilog__main.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_0 Bool)) (forall ((Verilog__main.LineState_o_64_0 (_ BitVec 2))) (forall ((Verilog__main.reset_64_1 Bool)) (forall ((Verilog__main.rst_64_1 Bool)) (forall ((Verilog__main.usb_rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_1 Bool)) (forall ((Verilog__main.clk_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_1 Bool)) (forall ((Verilog__main.fs_ce_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_1 Bool)) (forall ((Verilog__main.phy_tx_mode_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_1 Bool)) (forall ((Verilog__main.txdp_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_1 Bool)) (forall ((Verilog__main.txdn_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_1 Bool)) (forall ((Verilog__main.txoe_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_1 Bool)) (forall ((Verilog__main.TxValid_i_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_1 Bool)) (forall ((Verilog__main.TxReady_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_1 Bool)) (forall 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((Verilog__main.rst_64_2 Bool)) (forall ((Verilog__main.usb_rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_2 Bool)) (forall ((Verilog__main.clk_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_2 Bool)) (forall ((Verilog__main.phy_tx_mode_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_2 Bool)) (forall ((Verilog__main.txdp_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_2 Bool)) (forall ((Verilog__main.txdn_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_2 Bool)) (forall ((Verilog__main.txoe_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_2 Bool)) (forall ((Verilog__main.TxValid_i_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_2 Bool)) (forall ((Verilog__main.TxReady_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_2 Bool)) (forall ((Verilog__main.rxd_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_2 Bool)) (forall ((Verilog__main.rxdp_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_2 Bool)) (forall ((Verilog__main.rxdn_64_2 Bool)) (forall ((Verilog__main.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_2 Bool)) (forall ((Verilog__main.RxActive_o_64_2 Bool)) (forall ((Verilog__main.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_2 Bool)) (forall ((Verilog__main.LineState_o_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_0 Bool)) (forall ((Verilog__main.rst_cnt_64_0 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_1 Bool)) (forall ((Verilog__main.rst_cnt_64_1 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_2 Bool)) (forall ((Verilog__main.rst_cnt_64_2 (_ BitVec 5))) (exists ((Verilog__main.reset_64_0_39_ Bool)) (exists ((Verilog__main.rst_64_0_39_ Bool)) (exists ((Verilog__main.usb_rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_0_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_0_39_ Bool)) (exists ((Verilog__main.txdp_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_0_39_ Bool)) (exists ((Verilog__main.txdn_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_0_39_ Bool)) (exists ((Verilog__main.txoe_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_0_39_ Bool)) (exists ((Verilog__main.rxd_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Bool)) (exists ((Verilog__main.LineState_o_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.reset_64_1_39_ Bool)) (exists ((Verilog__main.rst_64_1_39_ Bool)) (exists ((Verilog__main.usb_rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_1_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_1_39_ Bool)) (exists ((Verilog__main.txdp_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_1_39_ Bool)) (exists ((Verilog__main.txdn_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_1_39_ Bool)) (exists ((Verilog__main.txoe_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_1_39_ Bool)) (exists ((Verilog__main.rxd_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Bool)) (exists ((Verilog__main.LineState_o_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_0_39_ (_ BitVec 5))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_1_39_ (_ BitVec 5))) (=> (and (and (= Verilog__main.reset_64_0 (and Verilog__main.rst_64_0 (not Verilog__main.usb_rst_64_0))) (and (= Verilog__main.i_tx_phy.hold_64_0 Verilog__main.i_tx_phy.stuff_64_0) (= Verilog__main.i_tx_phy.sft_done_e_64_0 (and Verilog__main.i_tx_phy.sft_done_64_0 (not Verilog__main.i_tx_phy.sft_done_r_64_0))) (= Verilog__main.i_tx_phy.stuff_64_0 (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0)) (= Verilog__main.i_tx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_tx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_tx_phy.phy_mode_64_0 Verilog__main.phy_tx_mode_64_0) (= Verilog__main.i_tx_phy.txdp_64_0 Verilog__main.txdp_64_0) (= Verilog__main.i_tx_phy.txdn_64_0 Verilog__main.txdn_64_0) (= Verilog__main.i_tx_phy.txoe_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.DataOut_i_64_0) (= Verilog__main.i_tx_phy.TxValid_i_64_0 Verilog__main.TxValid_i_64_0) (= Verilog__main.i_tx_phy.TxReady_o_64_0 Verilog__main.TxReady_o_64_0) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.i_rx_phy.rx_active_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.i_rx_phy.rx_valid_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 false) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.i_rx_phy.hold_reg_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) Verilog__main.i_rx_phy.rxdn_s_64_0)) (= Verilog__main.i_rx_phy.j_64_0 (and Verilog__main.i_rx_phy.rxdp_s_64_0 (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.se0_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (= Verilog__main.i_rx_phy.change_64_0 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0 Verilog__main.i_rx_phy.rxdp_s1_64_0) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0 Verilog__main.i_rx_phy.rxdn_s1_64_0))) (= Verilog__main.i_rx_phy.drop_bit_64_0 (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_rx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_rx_phy.rxd_64_0 Verilog__main.rxd_64_0) (= Verilog__main.i_rx_phy.rxdp_64_0 Verilog__main.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdn_64_0 Verilog__main.rxdn_64_0) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.DataIn_o_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.RxValid_o_64_0) (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.RxActive_o_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 Verilog__main.RxError_o_64_0) (= Verilog__main.i_rx_phy.RxEn_i_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 Verilog__main.LineState_o_64_0)) (and (= Verilog__main.reset_64_1 (and Verilog__main.rst_64_1 (not Verilog__main.usb_rst_64_1))) (and (= Verilog__main.i_tx_phy.hold_64_1 Verilog__main.i_tx_phy.stuff_64_1) (= Verilog__main.i_tx_phy.sft_done_e_64_1 (and Verilog__main.i_tx_phy.sft_done_64_1 (not Verilog__main.i_tx_phy.sft_done_r_64_1))) (= Verilog__main.i_tx_phy.stuff_64_1 (= Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1)) (= Verilog__main.i_tx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_tx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_tx_phy.phy_mode_64_1 Verilog__main.phy_tx_mode_64_1) (= Verilog__main.i_tx_phy.txdp_64_1 Verilog__main.txdp_64_1) (= Verilog__main.i_tx_phy.txdn_64_1 Verilog__main.txdn_64_1) (= Verilog__main.i_tx_phy.txoe_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.DataOut_i_64_1) (= Verilog__main.i_tx_phy.TxValid_i_64_1 Verilog__main.TxValid_i_64_1) (= Verilog__main.i_tx_phy.TxReady_o_64_1 Verilog__main.TxReady_o_64_1) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.i_rx_phy.rx_active_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.i_rx_phy.rx_valid_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 false) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.i_rx_phy.hold_reg_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) Verilog__main.i_rx_phy.rxdn_s_64_1)) (= Verilog__main.i_rx_phy.j_64_1 (and Verilog__main.i_rx_phy.rxdp_s_64_1 (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.se0_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (= Verilog__main.i_rx_phy.change_64_1 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_1) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_1))) (= Verilog__main.i_rx_phy.drop_bit_64_1 (= Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_rx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_rx_phy.rxd_64_1 Verilog__main.rxd_64_1) (= Verilog__main.i_rx_phy.rxdp_64_1 Verilog__main.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdn_64_1 Verilog__main.rxdn_64_1) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.DataIn_o_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.RxValid_o_64_1) (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.RxActive_o_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 Verilog__main.RxError_o_64_1) (= Verilog__main.i_rx_phy.RxEn_i_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 Verilog__main.LineState_o_64_1)) (and (= Verilog__main.reset_64_2 (and Verilog__main.rst_64_2 (not Verilog__main.usb_rst_64_2))) (and (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.stuff_64_2) (= Verilog__main.i_tx_phy.sft_done_e_64_2 (and Verilog__main.i_tx_phy.sft_done_64_2 (not Verilog__main.i_tx_phy.sft_done_r_64_2))) (= Verilog__main.i_tx_phy.stuff_64_2 (= Verilog__main.i_tx_phy.one_cnt_64_2 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_2)) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.phy_tx_mode_64_2) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.txdp_64_2) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.txdn_64_2) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.DataOut_i_64_2) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.TxValid_i_64_2) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.TxReady_o_64_2) (and (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.rx_active_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.rx_valid_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 false) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.hold_reg_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_2 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_2 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) Verilog__main.i_rx_phy.rxdn_s_64_2)) (= Verilog__main.i_rx_phy.j_64_2 (and Verilog__main.i_rx_phy.rxdp_s_64_2 (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.se0_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.rx_en_64_2) (= Verilog__main.i_rx_phy.change_64_2 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_2) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_2))) (= Verilog__main.i_rx_phy.drop_bit_64_2 (= Verilog__main.i_rx_phy.one_cnt_64_2 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.rxd_64_2) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.rxdp_64_2) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.rxdn_64_2) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.DataIn_o_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.RxValid_o_64_2) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.RxActive_o_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.RxError_o_64_2) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.LineState_o_64_2)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0 false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0 true) (= Verilog__main.i_tx_phy.append_eop_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0 false) (= Verilog__main.i_tx_phy.txoe_r1_64_0 false) (= Verilog__main.i_tx_phy.txoe_r2_64_0 false) (= Verilog__main.i_tx_phy.txdp_64_0 true) (= Verilog__main.i_tx_phy.txdn_64_0 false) (= Verilog__main.i_tx_phy.txoe_64_0 true) (= Verilog__main.i_tx_phy.TxReady_o_64_0 false) (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0 false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0 false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0 false) (= Verilog__main.i_tx_phy.ld_data_d_64_0 false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0 false) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0 false) (= Verilog__main.i_tx_phy.data_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_r_64_0 false) (= Verilog__main.i_tx_phy.ld_data_64_0 false) (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0 false) (= Verilog__main.i_rx_phy.rxd_t1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s_64_0 false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s_64_0 false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s_64_0 false) (= Verilog__main.i_rx_phy.synced_d_64_0 false) (= Verilog__main.i_rx_phy.rx_en_64_0 false) (= Verilog__main.i_rx_phy.rx_active_64_0 false) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0 false) (= Verilog__main.i_rx_phy.rx_valid_64_0 false) (= Verilog__main.i_rx_phy.shift_en_64_0 false) (= Verilog__main.i_rx_phy.sd_r_64_0 false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0 false) (= Verilog__main.i_rx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0 false) (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0 false)) (= Verilog__main.usb_rst_64_0 false) (= Verilog__main.rst_cnt_64_0 (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite Verilog__main.i_tx_phy.stuff_64_0 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (not Verilog__main.i_tx_phy.txoe_r1_64_0)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.sd_bs_o_64_0 Verilog__main.i_tx_phy.sd_nrzi_o_64_0 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0)))) (= Verilog__main.i_tx_phy.append_eop_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0 false Verilog__main.i_tx_phy.append_eop_64_0)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0))) (= Verilog__main.i_tx_phy.txoe_r1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0))) (= Verilog__main.i_tx_phy.txoe_r2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0))) (= Verilog__main.i_tx_phy.txdp_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.txdp_64_0))) (= Verilog__main.i_tx_phy.txdn_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.txdn_64_0))) (= Verilog__main.i_tx_phy.txoe_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (not (or Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0)) Verilog__main.i_tx_phy.txoe_64_0))) (= Verilog__main.i_tx_phy.TxReady_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0 Verilog__main.i_tx_phy.TxValid_i_64_0))) (= Verilog__main.i_tx_phy.state_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 (_ bv1 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 (_ bv3 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0 (_ bv5 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0) Verilog__main.i_tx_phy.fs_ce_64_0) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (_ bv0 3) Verilog__main.i_tx_phy.state_64_0) Verilog__main.i_tx_phy.state_64_0)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1 Verilog__main.i_tx_phy.tx_ready_d_64_0) (= Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.tx_ready_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_sop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_data_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_eop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 true (ite Verilog__main.i_tx_phy.eop_done_64_0 false Verilog__main.i_tx_phy.tx_ip_64_0)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0))) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0 (not Verilog__main.i_tx_phy.hold_64_0)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0)))) (= Verilog__main.i_tx_phy.hold_reg_64_1 (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0 Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.i_tx_phy.hold_reg_64_0))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0 (not Verilog__main.i_tx_phy.tx_ip_64_0)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0) false Verilog__main.i_tx_phy.data_done_64_0)))) (= Verilog__main.i_tx_phy.sft_done_64_1 (and (not Verilog__main.i_tx_phy.hold_64_0) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1 Verilog__main.i_tx_phy.sft_done_64_0) (= Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.ld_data_d_64_0) (= Verilog__main.i_tx_phy.one_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0) Verilog__main.i_tx_phy.stuff_64_0) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.fs_ce_r3_64_0) (= Verilog__main.i_rx_phy.rxd_t1_64_1 Verilog__main.i_rx_phy.rxd_64_0) (= Verilog__main.i_rx_phy.rxd_s1_64_1 Verilog__main.i_rx_phy.rxd_t1_64_0) (= Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.rxd_s1_64_0) (= Verilog__main.i_rx_phy.rxdp_t1_64_1 Verilog__main.i_rx_phy.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdp_s1_64_1 Verilog__main.i_rx_phy.rxdp_t1_64_0) (= Verilog__main.i_rx_phy.rxdp_s_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_t1_64_1 Verilog__main.i_rx_phy.rxdn_64_0) (= Verilog__main.i_rx_phy.rxdn_s1_64_1 Verilog__main.i_rx_phy.rxdn_t1_64_0) (= Verilog__main.i_rx_phy.rxdn_s_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.synced_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.synced_d_64_0 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1 Verilog__main.i_rx_phy.RxEn_i_64_0) (= Verilog__main.i_rx_phy.rx_active_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_en_64_0) true (ite (and Verilog__main.i_rx_phy.se0_64_0 Verilog__main.i_rx_phy.rx_valid_r_64_0) false Verilog__main.i_rx_phy.rx_active_64_0)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) false Verilog__main.i_rx_phy.rx_valid1_64_0)))) (= Verilog__main.i_rx_phy.rx_valid_64_1 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0) Verilog__main.i_rx_phy.rx_valid1_64_0) Verilog__main.i_rx_phy.fs_ce_64_0)) (= Verilog__main.i_rx_phy.shift_en_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (or Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_active_64_0) Verilog__main.i_rx_phy.shift_en_64_0)) (= Verilog__main.i_rx_phy.sd_r_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) Verilog__main.i_rx_phy.sd_nrzi_64_0))) (= Verilog__main.i_rx_phy.hold_reg_64_1 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.shift_en_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0)) Verilog__main.i_rx_phy.hold_reg_64_0)) (= Verilog__main.i_rx_phy.one_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0) Verilog__main.i_rx_phy.drop_bit_64_0) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0)))) (= Verilog__main.i_rx_phy.dpll_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.fs_ce_d_64_0 (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1 Verilog__main.i_rx_phy.fs_ce_d_64_0) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1 Verilog__main.i_rx_phy.fs_ce_r1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1 Verilog__main.i_rx_phy.fs_ce_r2_64_0) (= Verilog__main.i_rx_phy.fs_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0)))))))) Verilog__main.i_rx_phy.fs_state_64_0))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1 (ite Verilog__main.i_rx_phy.rx_valid_64_0 true (ite Verilog__main.i_rx_phy.fs_ce_64_0 false Verilog__main.i_rx_phy.rx_valid_r_64_0)))) (= Verilog__main.usb_rst_64_1 (= Verilog__main.rst_cnt_64_0 (_ bv31 5))) (= Verilog__main.rst_cnt_64_1 (ite (not Verilog__main.rst_64_0) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0) Verilog__main.fs_ce_64_0) (bvadd Verilog__main.rst_cnt_64_0 (_ bv1 5)) Verilog__main.rst_cnt_64_0))))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite Verilog__main.i_tx_phy.stuff_64_1 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_1 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_1))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (not Verilog__main.i_tx_phy.txoe_r1_64_1)) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.sd_bs_o_64_1 Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.sd_nrzi_o_64_1)))) (= Verilog__main.i_tx_phy.append_eop_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_1 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_1 false Verilog__main.i_tx_phy.append_eop_64_1)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1))) (= Verilog__main.i_tx_phy.txoe_r1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1))) (= Verilog__main.i_tx_phy.txoe_r2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1))) (= Verilog__main.i_tx_phy.txdp_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.txdp_64_1))) (= Verilog__main.i_tx_phy.txdn_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.txdn_64_1))) (= Verilog__main.i_tx_phy.txoe_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (not (or Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1)) Verilog__main.i_tx_phy.txoe_64_1))) (= Verilog__main.i_tx_phy.TxReady_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (and Verilog__main.i_tx_phy.tx_ready_d_64_1 Verilog__main.i_tx_phy.TxValid_i_64_1))) (= Verilog__main.i_tx_phy.state_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 (_ bv1 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 (_ bv3 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) (_ bv4 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_1 (_ bv5 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_1) Verilog__main.i_tx_phy.fs_ce_64_1) (_ bv6 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (_ bv0 3) Verilog__main.i_tx_phy.state_64_1) Verilog__main.i_tx_phy.state_64_1)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 true (ite Verilog__main.i_tx_phy.eop_done_64_1 false Verilog__main.i_tx_phy.tx_ip_64_1)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1))) (= Verilog__main.i_tx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_1 (not Verilog__main.i_tx_phy.hold_64_1)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_1)))) (= Verilog__main.i_tx_phy.hold_reg_64_2 (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.i_tx_phy.hold_reg_64_1))) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_1)))))))))) (= Verilog__main.i_tx_phy.data_done_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_1 (not Verilog__main.i_tx_phy.tx_ip_64_1)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_1) false Verilog__main.i_tx_phy.data_done_64_1)))) (= Verilog__main.i_tx_phy.sft_done_64_2 (and (not Verilog__main.i_tx_phy.hold_64_1) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_64_1) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1) (= Verilog__main.i_tx_phy.one_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_1) Verilog__main.i_tx_phy.stuff_64_1) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_1))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_64_1) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_64_1) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.synced_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.synced_d_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_1 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1) (= Verilog__main.i_rx_phy.rx_active_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_en_64_1) true (ite (and Verilog__main.i_rx_phy.se0_64_1 Verilog__main.i_rx_phy.rx_valid_r_64_1) false Verilog__main.i_rx_phy.rx_active_64_1)))) (= Verilog__main.i_rx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_1)))) (= Verilog__main.i_rx_phy.rx_valid1_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) false Verilog__main.i_rx_phy.rx_valid1_64_1)))) (= Verilog__main.i_rx_phy.rx_valid_64_2 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_1) Verilog__main.i_rx_phy.rx_valid1_64_1) Verilog__main.i_rx_phy.fs_ce_64_1)) (= Verilog__main.i_rx_phy.shift_en_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (or Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_active_64_1) Verilog__main.i_rx_phy.shift_en_64_1)) (= Verilog__main.i_rx_phy.sd_r_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.rx_active_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not (xor Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) Verilog__main.i_rx_phy.sd_nrzi_64_1))) (= Verilog__main.i_rx_phy.hold_reg_64_2 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.shift_en_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_1 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_1)) Verilog__main.i_rx_phy.hold_reg_64_1)) (= Verilog__main.i_rx_phy.one_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_1) Verilog__main.i_rx_phy.drop_bit_64_1) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_1)))) (= Verilog__main.i_rx_phy.dpll_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_1)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1) (= Verilog__main.i_rx_phy.fs_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_1) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_1)))))))) Verilog__main.i_rx_phy.fs_state_64_1))) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 (ite Verilog__main.i_rx_phy.rx_valid_64_1 true (ite Verilog__main.i_rx_phy.fs_ce_64_1 false Verilog__main.i_rx_phy.rx_valid_r_64_1)))) (= Verilog__main.usb_rst_64_2 (= Verilog__main.rst_cnt_64_1 (_ bv31 5))) (= Verilog__main.rst_cnt_64_2 (ite (not Verilog__main.rst_64_1) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_1 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_1) Verilog__main.fs_ce_64_1) (bvadd Verilog__main.rst_cnt_64_1 (_ bv1 5)) Verilog__main.rst_cnt_64_1)))))) (and (and (and (= Verilog__main.reset_64_0_39_ (and Verilog__main.rst_64_0_39_ (not Verilog__main.usb_rst_64_0_39_))) (and (= Verilog__main.i_tx_phy.hold_64_0_39_ Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (and Verilog__main.i_tx_phy.sft_done_64_0_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_0_39_))) (= Verilog__main.i_tx_phy.stuff_64_0_39_ (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_)) (= Verilog__main.i_tx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_0_39_ Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_0_39_ Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_0_39_ Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Verilog__main.TxReady_o_64_0_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) Verilog__main.i_rx_phy.rxdn_s_64_0_39_)) (= Verilog__main.i_rx_phy.j_64_0_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_0_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.se0_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_0_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_0_39_ (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_0_39_ Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_0_39_ Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_0_39_ Verilog__main.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ Verilog__main.LineState_o_64_0_39_)) (and (= Verilog__main.reset_64_1_39_ (and Verilog__main.rst_64_1_39_ (not Verilog__main.usb_rst_64_1_39_))) (and (= Verilog__main.i_tx_phy.hold_64_1_39_ Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_1_39_ (and Verilog__main.i_tx_phy.sft_done_64_1_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_1_39_))) (= Verilog__main.i_tx_phy.stuff_64_1_39_ (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_)) (= Verilog__main.i_tx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_1_39_ Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_1_39_ Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_1_39_ Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_1_39_ Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Verilog__main.TxReady_o_64_1_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) Verilog__main.i_rx_phy.rxdn_s_64_1_39_)) (= Verilog__main.i_rx_phy.j_64_1_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_1_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.se0_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.lock_en_64_1_39_ Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_1_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_1_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_1_39_ (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_1_39_ Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_1_39_ Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_1_39_ Verilog__main.rxdn_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ Verilog__main.LineState_o_64_1_39_)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ true) (= Verilog__main.i_tx_phy.append_eop_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r1_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r2_64_0_39_ false) (= Verilog__main.i_tx_phy.txdp_64_0_39_ true) (= Verilog__main.i_tx_phy.txdn_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_64_0_39_ true) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ false) (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ false) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ false) (= Verilog__main.i_tx_phy.data_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_r_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_64_0_39_ false) (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s_64_0_39_ false) (= Verilog__main.i_rx_phy.synced_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_en_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_active_64_0_39_ false) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_valid_64_0_39_ false) (= Verilog__main.i_rx_phy.shift_en_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_r_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ false) (= Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ false)) (= Verilog__main.usb_rst_64_0_39_ false) (= Verilog__main.rst_cnt_64_0_39_ (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite Verilog__main.i_tx_phy.stuff_64_0_39_ false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0_39_))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (not Verilog__main.i_tx_phy.txoe_r1_64_0_39_)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false Verilog__main.i_tx_phy.append_eop_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_))) (= Verilog__main.i_tx_phy.txdp_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.txdp_64_0_39_))) (= Verilog__main.i_tx_phy.txdn_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.txdn_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not (or Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_)) Verilog__main.i_tx_phy.txoe_64_0_39_))) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Verilog__main.i_tx_phy.TxValid_i_64_0_39_))) (= Verilog__main.i_tx_phy.state_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (_ bv1 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (_ bv3 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ (_ bv5 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0_39_) Verilog__main.i_tx_phy.fs_ce_64_0_39_) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (_ bv0 3) Verilog__main.i_tx_phy.state_64_0_39_) Verilog__main.i_tx_phy.state_64_0_39_)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1_39_ Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_data_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ false Verilog__main.i_tx_phy.tx_ip_64_0_39_)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_))) (= Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not Verilog__main.i_tx_phy.hold_64_0_39_)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_tx_phy.hold_reg_64_1_39_ (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0_39_ Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.i_tx_phy.hold_reg_64_0_39_))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0_39_)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (not Verilog__main.i_tx_phy.tx_ip_64_0_39_)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0_39_) false Verilog__main.i_tx_phy.data_done_64_0_39_)))) (= Verilog__main.i_tx_phy.sft_done_64_1_39_ (and (not Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_1_39_ Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) Verilog__main.i_tx_phy.stuff_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0_39_))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_1_39_ Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.synced_d_64_0_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0_39_ true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1_39_ Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) true (ite (and Verilog__main.i_rx_phy.se0_64_0_39_ Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) false Verilog__main.i_rx_phy.rx_active_64_0_39_)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) false Verilog__main.i_rx_phy.rx_valid1_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid_64_1_39_ (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0_39_) Verilog__main.i_rx_phy.rx_valid1_64_0_39_) Verilog__main.i_rx_phy.fs_ce_64_0_39_)) (= Verilog__main.i_rx_phy.shift_en_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (or Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) Verilog__main.i_rx_phy.shift_en_64_0_39_)) (= Verilog__main.i_rx_phy.sd_r_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) Verilog__main.i_rx_phy.sd_nrzi_64_0_39_))) (= Verilog__main.i_rx_phy.hold_reg_64_1_39_ (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.shift_en_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) Verilog__main.i_rx_phy.drop_bit_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.dpll_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0_39_)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0_39_) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0_39_)))))))) Verilog__main.i_rx_phy.fs_state_64_0_39_))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ (ite Verilog__main.i_rx_phy.rx_valid_64_0_39_ true (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ false Verilog__main.i_rx_phy.rx_valid_r_64_0_39_)))) (= Verilog__main.usb_rst_64_1_39_ (= Verilog__main.rst_cnt_64_0_39_ (_ bv31 5))) (= Verilog__main.rst_cnt_64_1_39_ (ite (not Verilog__main.rst_64_0_39_) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0_39_ (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0_39_) Verilog__main.fs_ce_64_0_39_) (bvadd Verilog__main.rst_cnt_64_0_39_ (_ bv1 5)) Verilog__main.rst_cnt_64_0_39_)))))) (or (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_0_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_0_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_0_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_0_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_0_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_0_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_0_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_0_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_0_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_0_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_0_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_0_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_0_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_0_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_0_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_0_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_0_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_0_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_0_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_0_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_0_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_0_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_0_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_0_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_0_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_0_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_0_39_)) (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_1_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_1_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_1_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_1_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_1_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_1_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_1_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_1_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_1_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_1_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_1_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_1_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_1_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_1_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_1_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_1_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_1_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_1_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_1_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_1_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_1_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_1_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_1_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_1_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_1_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_1_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_1_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_1_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_1_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_1_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_1_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_1_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_1_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_1_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_1_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_1_39_))))) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ))
diff --git a/test/regress/regress1/quantifiers/bug_743.smt2 b/test/regress/regress1/quantifiers/bug_743.smt2
index 1b6b16535..8b20cf5ca 100644
--- a/test/regress/regress1/quantifiers/bug_743.smt2
+++ b/test/regress/regress1/quantifiers/bug_743.smt2
@@ -4,7 +4,7 @@
 ;; produced by cvc4_14.drv ;;
 (set-logic AUFBVDTNIRA)
 (set-info :source |VC generated by SPARK 2014|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category industrial)
 (set-info :status unsat)
 ;;; generated by SMT-LIB2 driver
diff --git a/test/regress/regress1/quantifiers/burns13.smt2 b/test/regress/regress1/quantifiers/burns13.smt2
index 3424c161e..592187f9d 100644
--- a/test/regress/regress1/quantifiers/burns13.smt2
+++ b/test/regress/regress1/quantifiers/burns13.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: unsat
 (set-logic AUFLIA)
 (set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo  de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun s_0 (Int) Bool)
diff --git a/test/regress/regress1/quantifiers/burns4.smt2 b/test/regress/regress1/quantifiers/burns4.smt2
index 72023fd4f..1601b101e 100644
--- a/test/regress/regress1/quantifiers/burns4.smt2
+++ b/test/regress/regress1/quantifiers/burns4.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: unsat
 (set-logic AUFLIA)
 (set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo  de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun s_0 (Int) Bool)
diff --git a/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2 b/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2
index e9f0490a6..f9386005d 100644
--- a/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2
+++ b/test/regress/regress1/quantifiers/gauss_init_0030.fof.smt2
@@ -5,7 +5,7 @@ Aerospace Software", IJCAR 2004.  Translated from TPTP format by Yeting Ge and
 Clark Barrett
 
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun def () Real)
diff --git a/test/regress/regress1/quantifiers/issue3316.smt2 b/test/regress/regress1/quantifiers/issue3316.smt2
index 320a57790..0e69410f7 100644
--- a/test/regress/regress1/quantifiers/issue3316.smt2
+++ b/test/regress/regress1/quantifiers/issue3316.smt2
@@ -1,16 +1,9 @@
 ; COMMAND-LINE: --fmf-fun-rlv --no-check-models
 ; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String)))
-                       (a1(c1$0)(c1$1)(c1$2))
-                       (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool)))
-                       (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String)))
-                       (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2))
-                       (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6))
-                       (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6))
-                       (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool)))))
 (define-funs-rec ((f3((v4 Bool))a7)
                   (f2()a6)
                   (f1((v1 a3)(v2 a1)(v3 Bool))String)
diff --git a/test/regress/regress1/quantifiers/issue3317.smt2 b/test/regress/regress1/quantifiers/issue3317.smt2
index 57b353e28..758878af2 100644
--- a/test/regress/regress1/quantifiers/issue3317.smt2
+++ b/test/regress/regress1/quantifiers/issue3317.smt2
@@ -1,9 +1,9 @@
 ; COMMAND-LINE: --fmf-fun-rlv --no-check-models
 ; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
-(declare-datatypes () ((a0(c0$0(c0$0$0 a4)(c0$0$1 Bool)(c0$0$2 a4)(c0$0$3 Int)(c0$0$4 a5)(c0$0$5 a7)(c0$0$6 a7)))(a1(c1$0(c1$0$0 Bool)(c1$0$1 Bool)(c1$0$2 Int))(c1$1)(c1$2(c1$2$0 a3)(c1$2$1 a5)(c1$2$2 a1)(c1$2$3 a7))(c1$3)(c1$4)(c1$5)(c1$6)(c1$7)(c1$8)(c1$9(c1$9$0 a4))(c1$a))(a2(c2$0(c2$0$0 String)(c2$0$1 a4)(c2$0$2 a0)(c2$0$3 Bool)(c2$0$4 a5)(c2$0$5 a4))(c2$1)(c2$2)(c2$3)(c2$4)(c2$5))(a3(c3$0)(c3$1)(c3$2)(c3$3)(c3$4(c3$4$0 a6))(c3$5)(c3$6)(c3$7))(a4(c4$0)(c4$1(c4$1$0 a3))(c4$2(c4$2$0 a5))(c4$3)(c4$4)(c4$5(c4$5$0 String)(c4$5$1 a4))(c4$6)(c4$7)(c4$8)(c4$9(c4$9$0 String))(c4$a)(c4$b))(a5(c5$0)(c5$1(c5$1$0 a7)(c5$1$1 a0)(c5$1$2 Bool)(c5$1$3 a1)(c5$1$4 a3)(c5$1$5 a7)(c5$1$6 Int)(c5$1$7 Bool))(c5$2)(c5$3)(c5$4)(c5$5)(c5$6)(c5$7))(a6(c6$0(c6$0$0 Bool))(c6$1)(c6$2(c6$2$0 Bool)(c6$2$1 a3)(c6$2$2 Int)(c6$2$3 a3)(c6$2$4 a6)(c6$2$5 a7)(c6$2$6 a0)(c6$2$7 a6)))(a7(c7$0)(c7$1)(c7$2(c7$2$0 a6))(c7$3)(c7$4)(c7$5(c7$5$0 a2)(c7$5$1 a2)(c7$5$2 Int)(c7$5$3 a6))(c7$6)(c7$7))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0 (c0$0$0 a4) (c0$0$1 Bool) (c0$0$2 a4) (c0$0$3 Int) (c0$0$4 a5) (c0$0$5 a7) (c0$0$6 a7)))((c1$0 (c1$0$0 Bool) (c1$0$1 Bool) (c1$0$2 Int)) (c1$1) (c1$2 (c1$2$0 a3) (c1$2$1 a5) (c1$2$2 a1) (c1$2$3 a7)) (c1$3) (c1$4) (c1$5) (c1$6) (c1$7) (c1$8) (c1$9 (c1$9$0 a4)) (c1$a))((c2$0 (c2$0$0 String) (c2$0$1 a4) (c2$0$2 a0) (c2$0$3 Bool) (c2$0$4 a5) (c2$0$5 a4)) (c2$1) (c2$2) (c2$3) (c2$4) (c2$5))((c3$0) (c3$1) (c3$2) (c3$3) (c3$4 (c3$4$0 a6)) (c3$5) (c3$6) (c3$7))((c4$0) (c4$1 (c4$1$0 a3)) (c4$2 (c4$2$0 a5)) (c4$3) (c4$4) (c4$5 (c4$5$0 String) (c4$5$1 a4)) (c4$6) (c4$7) (c4$8) (c4$9 (c4$9$0 String)) (c4$a) (c4$b))((c5$0) (c5$1 (c5$1$0 a7) (c5$1$1 a0) (c5$1$2 Bool) (c5$1$3 a1) (c5$1$4 a3) (c5$1$5 a7) (c5$1$6 Int) (c5$1$7 Bool)) (c5$2) (c5$3) (c5$4) (c5$5) (c5$6) (c5$7))((c6$0 (c6$0$0 Bool)) (c6$1) (c6$2 (c6$2$0 Bool) (c6$2$1 a3) (c6$2$2 Int) (c6$2$3 a3) (c6$2$4 a6) (c6$2$5 a7) (c6$2$6 a0) (c6$2$7 a6)))((c7$0) (c7$1) (c7$2 (c7$2$0 a6)) (c7$3) (c7$4) (c7$5 (c7$5$0 a2) (c7$5$1 a2) (c7$5$2 Int) (c7$5$3 a6)) (c7$6) (c7$7))))
 (define-funs-rec ( (f9((v38 Int)(v39 a2)(v3a a5)(v3b a0)(v3c a7)(v3d a3))Bool)
                    (f8((v33 String)(v34 Int)(v35 a1)(v36 a7)(v37 a4))a6)
                    (f7((v29 a1)(v2a Bool)(v2b a3)(v2c String)(v2d Bool)(v2e String)(v2f a7)(v30 a5)(v31 a2)(v32 a2))Int)
diff --git a/test/regress/regress1/quantifiers/issue3765.smt2 b/test/regress/regress1/quantifiers/issue3765.smt2
index 97e106365..4947586f2 100644
--- a/test/regress/regress1/quantifiers/issue3765.smt2
+++ b/test/regress/regress1/quantifiers/issue3765.smt2
@@ -1,7 +1,7 @@
 ; COMMAND-LINE: --fmf-fun --no-check-models
 ; EXPECT: sat
 
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
 (define-funs-rec (
diff --git a/test/regress/regress1/quantifiers/issue993.smt2 b/test/regress/regress1/quantifiers/issue993.smt2
index 40c5538de..aa0c29f5e 100644
--- a/test/regress/regress1/quantifiers/issue993.smt2
+++ b/test/regress/regress1/quantifiers/issue993.smt2
@@ -1,5 +1,5 @@
 (set-logic AUFBVDTNIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status unsat)
 (declare-sort us_private 0)
 
@@ -7,18 +7,13 @@
 
 (declare-fun to_rep1 (integer) Int)
 
-(declare-datatypes ()
-((us_split_fields
- (mk___split_fields (rec__unit1__t1__c1 integer)(rec__ext__ us_private)))))
+(declare-datatypes ((us_split_fields 0)) (((mk___split_fields (rec__unit1__t1__c1 integer) (rec__ext__ us_private)))))
+(declare-datatypes ((us_split_fields__ref 0)) (((mk___split_fields__ref (us_split_fields__content us_split_fields)))))
 
-(declare-datatypes ()
-((us_split_fields__ref
- (mk___split_fields__ref (us_split_fields__content us_split_fields)))))
 (define-fun us_split_fields__ref___projection ((a us_split_fields__ref)) us_split_fields 
   (us_split_fields__content a))
 
-(declare-datatypes ()
-((us_rep (mk___rep (us_split_fields1 us_split_fields)(attr__tag Int)))))
+(declare-datatypes ((us_rep 0)) (((mk___rep (us_split_fields1 us_split_fields) (attr__tag Int)))))
 (define-fun us_rep___projection ((a us_rep)) us_split_fields (us_split_fields1
                                                              a))
 
@@ -34,19 +29,13 @@
      (= (to_rep1 (rec__unit1__t1__c1 (us_split_fields1 x))) 0))) :pattern (
   (is_zero x)) )))
 
-(declare-datatypes ()
-((us_split_fields2
- (mk___split_fields1
- (rec__unit2__t2__c2 integer)(rec__unit1__t1__c11 integer)(rec__ext__1 us_private)))))
+(declare-datatypes ((us_split_fields2 0)) (((mk___split_fields1 (rec__unit2__t2__c2 integer) (rec__unit1__t1__c11 integer) (rec__ext__1 us_private)))))
+(declare-datatypes ((us_split_fields__ref1 0)) (((mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2)))))
 
-(declare-datatypes ()
-((us_split_fields__ref1
- (mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2)))))
 (define-fun us_split_fields__ref_2__projection ((a us_split_fields__ref1)) us_split_fields2 
   (us_split_fields__content1 a))
 
-(declare-datatypes ()
-((us_rep1 (mk___rep1 (us_split_fields3 us_split_fields2)(attr__tag1 Int)))))
+(declare-datatypes ((us_rep1 0)) (((mk___rep1 (us_split_fields3 us_split_fields2) (attr__tag1 Int)))))
 (define-fun us_rep_3__projection ((a us_rep1)) us_split_fields2 (us_split_fields3
                                                                 a))
 
diff --git a/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2 b/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2
index 1c3aa1d8b..03ae9fb62 100644
--- a/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2
+++ b/test/regress/regress1/quantifiers/javafe.ast.StmtVec.009.smt2
@@ -3,7 +3,7 @@
   Simplify front end test suite.
   This benchmark was translated by Michal Moskal.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun after_133.8_133.8 () Int)
diff --git a/test/regress/regress1/quantifiers/opisavailable-12.smt2 b/test/regress/regress1/quantifiers/opisavailable-12.smt2
index c529b409f..879fbf4e4 100644
--- a/test/regress/regress1/quantifiers/opisavailable-12.smt2
+++ b/test/regress/regress1/quantifiers/opisavailable-12.smt2
@@ -2,7 +2,7 @@
 (set-info :source |
       Tokeneer case study <http://www.adacore.com/home/products/gnatpro/tokeneer/>
   |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun field.datat.length () Int)
diff --git a/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2 b/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2
index 2a5eb34a7..20ab505d4 100644
--- a/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2
+++ b/test/regress/regress1/quantifiers/qcft-javafe.filespace.TreeWalker.006.smt2
@@ -5,7 +5,7 @@
   Simplify front end test suite.
   This benchmark was translated by Michal Moskal.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun EC_134.22_134.22 () Int)
diff --git a/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2 b/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2
index 6874c522e..a5e893d9b 100644
--- a/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2
+++ b/test/regress/regress1/quantifiers/qcft-smtlib3dbc51.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: unsat
 (set-logic AUFLIRA)
 (set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort Unit 0)
diff --git a/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2 b/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2
index ec49231e3..3ce3b8406 100644
--- a/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2
+++ b/test/regress/regress1/quantifiers/rew-to-0211-dd.smt2
@@ -1,5 +1,5 @@
 (set-logic UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun boolIff (Int Int) Int)
diff --git a/test/regress/regress1/quantifiers/ricart-agrawala6.smt2 b/test/regress/regress1/quantifiers/ricart-agrawala6.smt2
index 5f849de15..b6ba41b0e 100644
--- a/test/regress/regress1/quantifiers/ricart-agrawala6.smt2
+++ b/test/regress/regress1/quantifiers/ricart-agrawala6.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIA)
 (set-info :source | An Optimal Algorithm for Mutual Exclusion in Computer Networks. Glenn Ricart and Ashok K. Agrawala. Communications of the ACM Vol.: 24 Number: 1. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo  de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-fun p () Int)
diff --git a/test/regress/regress1/quantifiers/set3.smt2 b/test/regress/regress1/quantifiers/set3.smt2
index bd208c6d3..ce5665f86 100644
--- a/test/regress/regress1/quantifiers/set3.smt2
+++ b/test/regress/regress1/quantifiers/set3.smt2
@@ -1,7 +1,7 @@
 ; COMMAND-LINE: --full-saturate-quant
 (set-logic AUFLIA)
 (set-info :source | Assertion verification of simple set manipulation programs. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-sort Set 0)
diff --git a/test/regress/regress1/quantifiers/set8.smt2 b/test/regress/regress1/quantifiers/set8.smt2
index 684d94b7a..bf0bb7130 100644
--- a/test/regress/regress1/quantifiers/set8.smt2
+++ b/test/regress/regress1/quantifiers/set8.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIA)
 (set-info :source | Set theory. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-sort Set 0)
diff --git a/test/regress/regress1/quantifiers/smtlib384a03.smt2 b/test/regress/regress1/quantifiers/smtlib384a03.smt2
index 9e2273cff..af68776b2 100644
--- a/test/regress/regress1/quantifiers/smtlib384a03.smt2
+++ b/test/regress/regress1/quantifiers/smtlib384a03.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIRA)
 (set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort Unit 0)
diff --git a/test/regress/regress1/quantifiers/smtlib46f14a.smt2 b/test/regress/regress1/quantifiers/smtlib46f14a.smt2
index fa0c85470..c550b308e 100644
--- a/test/regress/regress1/quantifiers/smtlib46f14a.smt2
+++ b/test/regress/regress1/quantifiers/smtlib46f14a.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIRA)
 (set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort Unit 0)
diff --git a/test/regress/regress1/quantifiers/smtlibf957ea.smt2 b/test/regress/regress1/quantifiers/smtlibf957ea.smt2
index aa82255ef..1d6a7f577 100644
--- a/test/regress/regress1/quantifiers/smtlibf957ea.smt2
+++ b/test/regress/regress1/quantifiers/smtlibf957ea.smt2
@@ -1,6 +1,6 @@
 (set-logic AUFLIRA)
 (set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort Unit 0)
diff --git a/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2 b/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2
index ebf1f080e..ba5d012a0 100644
--- a/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2
+++ b/test/regress/regress1/quantifiers/symmetric_unsat_7.smt2
@@ -3,7 +3,7 @@
 (set-info :source | Example extracted from Peter Baumgartner's talk at CADE-21: Logical Engineering with Instance-Based Methods.
 
 It was translated to SMT-LIB by Leonardo de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-fun symmetric ((Array Int (Array Int Real)) Int) Bool)
diff --git a/test/regress/regress1/quantifiers/var-eq-trigger.smt2 b/test/regress/regress1/quantifiers/var-eq-trigger.smt2
index bccc86e6f..970fea047 100644
--- a/test/regress/regress1/quantifiers/var-eq-trigger.smt2
+++ b/test/regress/regress1/quantifiers/var-eq-trigger.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: unsat
 (set-logic UFNIA)
 (set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011.  Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status unsat)
 (declare-sort S1 0)
diff --git a/test/regress/regress1/sets/fuzz14418.smt2 b/test/regress/regress1/sets/fuzz14418.smt2
index 24679749c..9b65102a6 100644
--- a/test/regress/regress1/sets/fuzz14418.smt2
+++ b/test/regress/regress1/sets/fuzz14418.smt2
@@ -8,7 +8,7 @@
 ;
 ; sat
 (set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (set-logic QF_UFLIAFS)
diff --git a/test/regress/regress1/sets/fuzz15201.smt2 b/test/regress/regress1/sets/fuzz15201.smt2
index e12b74d18..f9dbaeb75 100644
--- a/test/regress/regress1/sets/fuzz15201.smt2
+++ b/test/regress/regress1/sets/fuzz15201.smt2
@@ -1,7 +1,7 @@
 ; symptom: unsat instead of sat
 ; issue/fix: buggy rewriter for setminus
 (set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (set-logic QF_UFLIAFS)
diff --git a/test/regress/regress1/sets/fuzz31811.smt2 b/test/regress/regress1/sets/fuzz31811.smt2
index 5e7c032ea..9a7a7510a 100644
--- a/test/regress/regress1/sets/fuzz31811.smt2
+++ b/test/regress/regress1/sets/fuzz31811.smt2
@@ -6,7 +6,7 @@
 ; stop.
 ; 
 (set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (set-logic QF_UFLIAFS)
diff --git a/test/regress/regress1/sets/sharingbug.smt2 b/test/regress/regress1/sets/sharingbug.smt2
index b87579816..82c6eb8f0 100644
--- a/test/regress/regress1/sets/sharingbug.smt2
+++ b/test/regress/regress1/sets/sharingbug.smt2
@@ -1,5 +1,5 @@
 (set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "random")
 (set-info :status sat)
 (set-logic QF_UFLIAFS)
diff --git a/test/regress/regress1/strings/bug686dd.smt2 b/test/regress/regress1/strings/bug686dd.smt2
index b5c9457ff..1449a09be 100644
--- a/test/regress/regress1/strings/bug686dd.smt2
+++ b/test/regress/regress1/strings/bug686dd.smt2
@@ -1,14 +1,13 @@
-(set-info :smt-lib-version 2.5)
 (set-logic UFDTSLIA)
 (set-info :status sat)
 
-(declare-datatypes () ((T (TC (TCb String)))))
+(declare-datatype T ((TC (TCb String))))
 
 (declare-fun root5 () String)
 (declare-fun root6 () T)
 
 (assert (and 
-(str.in.re root5 ((_ re.loop 4 4) (re.range "0" "9")) )
-(str.in.re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) )
+(str.in_re root5 ((_ re.loop 4 4) (re.range "0" "9")) )
+(str.in_re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) )
 ) )
 (check-sat)
diff --git a/test/regress/regress1/strings/issue1105.smt2 b/test/regress/regress1/strings/issue1105.smt2
index bf5cb7669..59f618403 100644
--- a/test/regress/regress1/strings/issue1105.smt2
+++ b/test/regress/regress1/strings/issue1105.smt2
@@ -1,11 +1,10 @@
-(set-info :smt-lib-version 2.5)
 (set-logic ALL)
 (set-option :strings-exp true)
 (set-info :status sat)
-(declare-datatypes () ((Val
-    (Str (str String))
-    (Num (num Int)))))
+(declare-datatype Val
+    ((Str (str String))
+    (Num (num Int))))
 
 (declare-const var0 Val)
-(assert (=> (is-Str var0) (distinct (str.to.int (str var0)) (- 1))))
+(assert (=> (is-Str var0) (distinct (str.to_int (str var0)) (- 1))))
 (check-sat)
diff --git a/test/regress/regress1/strings/issue1684-regex.smt2 b/test/regress/regress1/strings/issue1684-regex.smt2
index de0739bd8..41fa27120 100644
--- a/test/regress/regress1/strings/issue1684-regex.smt2
+++ b/test/regress/regress1/strings/issue1684-regex.smt2
@@ -1,8 +1,8 @@
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-logic QF_S)
 (set-info :status sat)
 (set-option :strings-exp true)
 (declare-const s String)
-(assert (str.in.re s (re.* (re.range "\x00" "\xFF"))))
-(assert (str.in.re s (re.range "\x00" "\xFF")))
+(assert (str.in_re s (re.* (re.range "\u{0}" "\u{ff}"))))
+(assert (str.in_re s (re.range "\u{0}" "\u{ff}")))
 (check-sat)
diff --git a/test/regress/regress1/strings/issue3272.smt2 b/test/regress/regress1/strings/issue3272.smt2
index cf33afb92..622e294d8 100644
--- a/test/regress/regress1/strings/issue3272.smt2
+++ b/test/regress/regress1/strings/issue3272.smt2
@@ -1,4 +1,4 @@
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-logic ALL_SUPPORTED)
 (set-option :strings-exp true)
 (set-info :status sat)
@@ -9,13 +9,13 @@
     (and              
         (and                                      
             (and                          
-                (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\t") 1 0) 0))   
+                (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\u{9}") 1 0) 0))   
                    
                 (= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) "B") 1 0) 0)
             )     
                             
             (= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len c) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) " ") 1 0) 0)                   
-            (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\v") 1 0) 0))
+            (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\u{b}") 1 0) 0))
         )       
         (= (ite (= (str.at (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0) " ") 1 0) 0)
     )
diff --git a/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2 b/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2
index b2bb29577..4879cb3fb 100644
--- a/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2
+++ b/test/regress/regress1/strings/issue3657-unexpectedUnsatCVC4.smt2
@@ -10,10 +10,10 @@
 ; EXPECT: sat
 ; EXPECT: sat
 ; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
 (set-option :produce-models true)
 (set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a1)(c0$3$1 Int)(c0$3$2 String)(c0$3$3 Int))(c0$4(c0$4$0 Int))(c0$5))(a1(c1$0(c1$0$0 a0)(c1$0$1 a0)(c1$0$2 String)(c1$0$3 Int))(c1$1(c1$1$0 Int))(c1$2)(c1$3(c1$3$0 Int))(c1$4)(c1$5))(a2(c2$0(c2$0$0 Int)(c2$0$1 a0))(c2$1(c2$1$0 String)(c2$1$1 a0)(c2$1$2 a1)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a1) (c0$3$1 Int) (c0$3$2 String) (c0$3$3 Int)) (c0$4 (c0$4$0 Int)) (c0$5))((c1$0 (c1$0$0 a0) (c1$0$1 a0) (c1$0$2 String) (c1$0$3 Int)) (c1$1 (c1$1$0 Int)) (c1$2) (c1$3 (c1$3$0 Int)) (c1$4) (c1$5))((c2$0 (c2$0$0 Int) (c2$0$1 a0)) (c2$1 (c2$1$0 String) (c2$1$1 a0) (c2$1$2 a1)))))
 (push 1)
 (pop 1)
 (push 1)
diff --git a/test/regress/regress1/strings/pierre150331.smt2 b/test/regress/regress1/strings/pierre150331.smt2
index ae4277874..562904366 100644
--- a/test/regress/regress1/strings/pierre150331.smt2
+++ b/test/regress/regress1/strings/pierre150331.smt2
@@ -1,13 +1,13 @@
-(set-info :smt-lib-version 2.5)
-(set-logic SLIA)
-(set-info :status sat)
-(set-option :strings-exp true)
-(define-fun stringEval ((?s String)) Bool (str.in.re ?s 
-(re.union 
-(str.to.re "H")
-(re.++ ((_ re.loop 2 2) (str.to.re "{") ) ((_ re.loop 2 4) (re.union re.nostr (re.range "" "]") (re.range "" "^") ) ) ) ) ) )
-(declare-fun s0() String)
-(declare-fun s1() String)
-(declare-fun s2() String)
-(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) )
-(check-sat)
+(set-info :smt-lib-version 2.6)
+(set-logic SLIA)
+(set-info :status sat)
+(set-option :strings-exp true)
+(define-fun stringEval ((?s String)) Bool (str.in_re ?s 
+(re.union 
+(str.to_re "H")
+(re.++ ((_ re.loop 2 2) (str.to_re "{") ) ((_ re.loop 2 4) (re.union re.none (re.range "\u{1d}" "]") (re.range "\u{e}" "^") ) ) ) ) ) )
+(declare-fun s0() String)
+(declare-fun s1() String)
+(declare-fun s2() String)
+(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) )
+(check-sat)
diff --git a/test/regress/regress1/uf2.smt2 b/test/regress/regress1/uf2.smt2
index 0aa1617eb..1dc17b045 100644
--- a/test/regress/regress1/uf2.smt2
+++ b/test/regress/regress1/uf2.smt2
@@ -1,5 +1,5 @@
 (set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "crafted")
 (set-info :status unsat)
 (declare-fun v1 () (_ BitVec 1))
diff --git a/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2 b/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2
index 84ed4b199..c18486fce 100644
--- a/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2
+++ b/test/regress/regress1/uflia/FIREFLY_3_e2_2236_e7_3681.ec.core.smt2
@@ -2,7 +2,7 @@
 ; EXPECT: sat
 
 (set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (declare-fun _base () Int)
 (declare-fun _n () Int)
 (declare-fun ___z3z___ (Int) Bool)
diff --git a/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2 b/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2
index 248a056d3..f7e670a2c 100644
--- a/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2
+++ b/test/regress/regress1/uflia/FIREFLY_luke_1b_e2_3049_e7_1173.ec.minimized.smt2
@@ -1,5 +1,5 @@
 (set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :status sat)
 (declare-fun _base () Int)
 (declare-fun _n () Int)
diff --git a/test/regress/regress1/uflia/simple_cyclic2.smt2 b/test/regress/regress1/uflia/simple_cyclic2.smt2
index 7a0b39999..57fd60b89 100644
--- a/test/regress/regress1/uflia/simple_cyclic2.smt2
+++ b/test/regress/regress1/uflia/simple_cyclic2.smt2
@@ -5,7 +5,7 @@ Benchmark generated from the verification of programs manipulating linked lists
 
 This benchmark was automatically translated into SMT-LIB format by Albert Oliveras.
 |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
 (set-info :category "industrial")
 (set-info :status sat)
 (declare-fun t.l () Int)
author	Mathias Preiner <mathias.preiner@gmail.com>	2021-03-05 16:17:15 -0800
committer	GitHub <noreply@github.com>	2021-03-06 00:17:15 +0000
commit	c6fffe4fd328401f7f7e0757303e8dea5f6c14a4 (patch)
tree	84bbb3f44fa7ffbeba0c0baf9b7b22f036d2e9f4 /test/regress/regress1
parent	555e4b0b6b10e9170676c0a3ef9b778322f3327f (diff)