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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2020-04-14 20:54:54 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-14 20:54:54 -0500 |
| commit | be6719144c88921fa39823976376961fe03f17a7 (patch) | |
| tree | 58e89856d0c44bda9dbdf4817e89e4f53bc7af55 /test/regress/regress1 | |
| parent | 073ee2672169a40163615811994c2140c982ff36 (diff) | |
Disable preregistration of instantiations for cegqi in incremental (#4251)
Fixes #4243.
Diffstat (limited to 'test/regress/regress1')
| -rw-r--r-- | test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2 | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2 b/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2 new file mode 100644 index 000000000..aa5cbc31e --- /dev/null +++ b/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2 @@ -0,0 +1,15 @@ +; COMMAND-LINE: -i +; EXPECT: sat +(set-logic BV) +(set-info :status sat) +(declare-fun _substvar_16_ () Bool) +(set-option :cbqi-prereg-inst true) +(set-option :check-models true) +(declare-fun v2 () Bool) +(push 1) +(assert (exists ((q1 (_ BitVec 12)) (q2 Bool) (q3 (_ BitVec 12))) (xor _substvar_16_ q2 v2))) +(push 1) +(pop 1) +(pop 1) +(assert (forall ((q23 (_ BitVec 6))) v2)) +(check-sat) |