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| author | ajreynol <andrew.j.reynolds@gmail.com> | 2016-10-21 14:01:17 -0500 |
|---|---|---|
| committer | ajreynol <andrew.j.reynolds@gmail.com> | 2016-10-21 14:01:17 -0500 |
| commit | 01d6e3933a3d733d3c1b5486ce1df8389cd6a176 (patch) | |
| tree | 3110c0a54c0466862da0c7537b90013dab6a6479 /test/regress/regress1/sygus | |
| parent | 3e93fdba8102e4ad1399af78967fec3d0495722a (diff) | |
Move slow regress0 benchmarks to regress1, increment regress1 through regress3.
Diffstat (limited to 'test/regress/regress1/sygus')
| -rw-r--r-- | test/regress/regress1/sygus/hd-sdiv.sy | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/regress/regress1/sygus/hd-sdiv.sy b/test/regress/regress1/sygus/hd-sdiv.sy new file mode 100644 index 000000000..019b48a1c --- /dev/null +++ b/test/regress/regress1/sygus/hd-sdiv.sy @@ -0,0 +1,16 @@ +; EXPECT: unsat +; COMMAND-LINE: --cegqi-si=none --no-dump-synth +(set-logic BV) + +(define-fun hd01 ((x (BitVec 32))) (BitVec 32) (bvand x #x00000001)) + +(synth-fun f ((x (BitVec 32))) (BitVec 32) + ((Start (BitVec 32) ((bvsdiv Start Start) + (bvand Start Start) + x + #x00000001)))) + +(declare-var y (BitVec 32)) +(constraint (= (hd01 y) (f y))) +(check-synth) + |