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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2021-06-02 14:31:00 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-02 14:31:00 -0500 |
| commit | fbeb277a50b4780f6603aee6be9265644a430a47 (patch) | |
| tree | 7536a3775b50dd78f978e5a0d982f64182273651 /test/regress/regress1/sygus/clock-inc-tuple.sy | |
| parent | adb0ca274a1294e251fa5bca030ad54406fe26df (diff) | |
| parent | 85a300898d7815973c064fe2c7b5b33473a71a5c (diff) | |
Merge branch 'master' into issue6661issue6661
Diffstat (limited to 'test/regress/regress1/sygus/clock-inc-tuple.sy')
| -rw-r--r-- | test/regress/regress1/sygus/clock-inc-tuple.sy | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/regress/regress1/sygus/clock-inc-tuple.sy b/test/regress/regress1/sygus/clock-inc-tuple.sy index b5d7bff91..5af4407f7 100644 --- a/test/regress/regress1/sygus/clock-inc-tuple.sy +++ b/test/regress/regress1/sygus/clock-inc-tuple.sy @@ -1,7 +1,7 @@ ; EXPECT: unsat ; COMMAND-LINE: --lang=sygus2 --sygus-si=all --sygus-out=status --decision=justification -(set-logic ALL_SUPPORTED) +(set-logic ALL) (declare-var m Int) (declare-var s Int) (declare-var inc Int) |