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author | Aina Niemetz <aina.niemetz@gmail.com> | 2017-12-20 18:27:39 -0800 |
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committer | GitHub <noreply@github.com> | 2017-12-20 18:27:39 -0800 |
commit | f9149d3b3e785950a846fb195bf9fa9cb1a2d94a (patch) | |
tree | c69c90377a6c24abbc9c608a767507740abfd3b6 /test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2 | |
parent | 13cc0e94ac8892fa1cefa53ff1c884d154894b58 (diff) |
Add explicit disequality handling when generating side condition for CBQI BV. (#1447)
This refactors solveBvLit to support explicit handling of disequalities (and, in the next step, inequalities) when generating side conditions.
Diffstat (limited to 'test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2')
-rw-r--r-- | test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2 | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2 b/test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2 deleted file mode 100644 index becfc5315..000000000 --- a/test/regress/regress0/quantifiers/qbv-test-invert-udiv-0.smt2 +++ /dev/null @@ -1,11 +0,0 @@ -; COMMAND-LINE: --cbqi-bv --bv-div-zero-const -; EXPECT: sat -(set-logic BV) -(set-info :status sat) -(declare-fun a () (_ BitVec 16)) -(declare-fun b () (_ BitVec 16)) - -(assert (distinct a b (_ bv0 16))) -(assert (forall ((x (_ BitVec 16))) (not (= (bvudiv x a) b)))) - -(check-sat) |