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| author | Andrew Reynolds <andrew.j.reynolds@gmail.com> | 2021-10-21 19:32:08 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-21 19:32:08 -0500 |
| commit | 81d4a2a0e337e341ac1373de0be8762617372ffc (patch) | |
| tree | eec38cb65373f9df09fde442fc69bd2088f7d005 /test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2 | |
| parent | 638c0bfdc798116925f839118dffd86581a58d43 (diff) | |
| parent | f9de5395d78bc5338ca800e539e91795730cbd29 (diff) | |
Merge branch 'master' into fixErrorSetfixErrorSet
Diffstat (limited to 'test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2')
| -rw-r--r-- | test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2 | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2 b/test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2 new file mode 100644 index 000000000..fcb26054e --- /dev/null +++ b/test/regress/regress0/preprocess/proj-issue305-circuit-prop-ite-b.smt2 @@ -0,0 +1,10 @@ +; EXPECT: sat +(set-logic ALL) +(set-option :check-proofs true) +(declare-fun a () Bool) +(declare-fun b () Bool) +(declare-fun c () Bool) +(assert c) +(assert (not b)) +(assert (ite a b c)) +(check-sat)
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