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| author | ajreynol <andrew.j.reynolds@gmail.com> | 2021-07-26 20:49:16 -0500 |
|---|---|---|
| committer | ajreynol <andrew.j.reynolds@gmail.com> | 2021-07-26 20:49:16 -0500 |
| commit | 5ffe05a0b2769ba0b4b338b19e21c818bc1047a7 (patch) | |
| tree | f4d835bafd1d2997668feda4cfd738b7f5672054 /test/regress/regress0/bv | |
| parent | 48254fd071805e1594fa4435e557391cf6795a05 (diff) | |
Miscellaneous sync to master
Diffstat (limited to 'test/regress/regress0/bv')
| -rw-r--r-- | test/regress/regress0/bv/bv_to_int_bvmul2.smt2 | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/regress/regress0/bv/bv_to_int_bvmul2.smt2 b/test/regress/regress0/bv/bv_to_int_bvmul2.smt2 index ebec5169a..91e0c45fd 100644 --- a/test/regress/regress0/bv/bv_to_int_bvmul2.smt2 +++ b/test/regress/regress0/bv/bv_to_int_bvmul2.smt2 @@ -2,9 +2,9 @@ ; EXPECT: unsat (set-logic QF_BV) (declare-fun T4_180 () (_ BitVec 32)) -(assert (and -(= (bvmul T4_180 (_ bv1056 32)) (_ bv0 32)) -(not (= (bvmul T4_180 (_ bv1408 32)) (_ bv0 32))) +(assert (and +(= (bvmul T4_180 (_ bv1056 32)) (_ bv0 32)) +(not (= (bvmul T4_180 (_ bv1408 32)) (_ bv0 32))) ) ) (check-sat) |